亲，“电路城论坛”已合并升级到更全、更大、更强的「新与非网」。了解「新与非网」

论坛

 注册/登录  
收藏本版 |订阅

FPGA/DSP 今日: 0|主题: 2858|排名: 5 

版主: stanauo
新窗 全部主题  最新  热门  热帖  精华  更多 
作者 回复/查看 最后发表
预览 Advanced Chip Design, Practical Examples in Verilog by Mr Kishore K Mishra zhang1998 2021-11-17 03889 zhang1998 2021-11-17 10:56
预览 SystemVerilog Verification UVM 1.1 Student & Lab Guide （可搜寻 PDF） zhang1998 2021-11-17 02745 zhang1998 2021-11-17 10:55
预览 Xilinx Vivado 2018.3 License attachment zhang1998 2021-11-17 0256 zhang1998 2021-11-17 10:53
预览 Cadence公司关于设计中很重要的Timing Closure问题的介绍和解... attachment zhang1998 2021-11-17 0206 zhang1998 2021-11-17 10:50
预览 很生动的CMOS工艺PPT+N阱工艺flash attachment zhang1998 2021-11-17 01540 zhang1998 2021-11-17 10:46
预览 MIPI CSI2 Tx 和 Rx 的 IP核 zhang1998 2021-11-17 01036 zhang1998 2021-11-17 10:45
预览 针对IIC主要是slave 的几个例子，verilog编写 attachment zhang1998 2021-11-17 0359 zhang1998 2021-11-17 10:44
预览 visio的circuit模板 attachment zhang1998 2021-11-17 0260 zhang1998 2021-11-17 10:43
预览 visio的circuit模板 attachment zhang1998 2021-11-17 0266 zhang1998 2021-11-17 10:41
预览 8255 verilog attachment zhang1998 2021-11-17 0390 zhang1998 2021-11-17 10:40
预览 8255 verilog attachment zhang1998 2021-11-17 0834 zhang1998 2021-11-17 10:39
预览 8255 verilog attachment zhang1998 2021-11-17 0381 zhang1998 2021-11-17 10:39
预览 贝尔实验室FPGA实现的**PPT：高性能加法器与乘法器的实... attachment zhang1998 2021-11-17 0358 zhang1998 2021-11-17 10:37
预览 Synopsys DC(Design Compiler) User Guide attachment zhang1998 2021-11-17 0432 zhang1998 2021-11-17 10:33
预览 Introduction to Digital Signal Processing using MatLab with App 2019 attachment zhang1998 2021-11-17 0967 zhang1998 2021-11-17 10:05
预览 最新版 Digital Design and Computer Architecture 最给力网盘下载 attachment zhang1998 2021-11-17 0382 zhang1998 2021-11-17 10:00
预览 推荐一本好书《FPGA权威指南(英文版).》 attachment zhang1998 2021-11-17 0365 zhang1998 2021-11-17 09:58
预览 sunburst-design迄今为止发表的所有文章 attachment zhang1998 2021-11-17 0232 zhang1998 2021-11-17 09:57
预览 25XX256 EEPROM verilog model attachment zhang1998 2021-11-17 0520 zhang1998 2021-11-17 09:56
预览 sifive_RISCV_开源verilog代码 attachment zhang1998 2021-11-17 03205 zhang1998 2021-11-17 09:54
预览 电子书：Designing Digital Computer Systems with Verilog.pdf attachment zhang1998 2021-11-17 0252 zhang1998 2021-11-17 09:52
预览 美光的DDR3的代码模型（通用） attachment zhang1998 2021-11-17 0987 zhang1998 2021-11-17 09:51
预览 多种算法的说明和源码(CORDIC,ECC,8B10B,AES......) attachment zhang1998 2021-11-17 01980 zhang1998 2021-11-17 09:50
预览 Aldec Active-HDL 10.2 x64 patched dll attachment zhang1998 2021-11-17 0333 zhang1998 2021-11-17 09:38
预览 xilinx vivado 2019.2 attachment zhang1998 2021-11-17 0399 zhang1998 2021-11-17 09:37
预览 《FPGA嵌入式项目开发三位一体实战精讲》 attachment zhang1998 2021-11-17 01747 zhang1998 2021-11-17 09:36
预览 《FPGA嵌入式项目开发三位一体实战精讲》 attachment zhang1998 2021-11-17 01445 zhang1998 2021-11-17 09:34
预览 A Practical Guide for Designing, Synthesizing, and Simulating经典!!! attachment zhang1998 2021-11-17 0211 zhang1998 2021-11-17 09:25
预览 Digital Design: Principles and Practices attachment zhang1998 2021-11-17 02390 zhang1998 2021-11-17 09:20
预览 中国台湾CIC培训教程-Astro attachment zhang1998 2021-11-17 0204 zhang1998 2021-11-17 09:18
下一页 »
1 ...282930313233343536... 96下一页
 返 回 发新帖

快速发帖

还可输入 80 个字符
高级模式
B Color Image Link Quote Code Smilies
您需要登录后才可以发帖 注册/登录

本版积分规则

关闭

站长推荐上一条 /2 下一条



手机版|小黑屋|与非网

GMT+8, 2024-12-26 08:39 , Processed in 0.074661 second(s), 7 queries , MemCache On.

ICP经营许可证 苏B2-20140176  苏ICP备14012660号-2   苏州灵动帧格网络科技有限公司 版权所有.

苏公网安备 32059002001037号

Powered by Discuz! X3.4

Copyright © 2001-2024, Tencent Cloud.