SystemVerilog Verification UVM 1.1 Student & Lab Guide （可搜寻 PDF）

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SV + UVM 是logic design & verification的未来

Systemverilog Verification UVM 1.1 Student & Lab Guide 2011.12（可搜寻 PDF）

At the end of this workshop the student should be able to:

• Develop UVM 1.1 tests
• Implement and manage report messages for printing to terminal or file
• Create random stimulus and sequences
• Build and manage stimulus sequencers, drivers and monitors
• Create configurable agents containing sequencer, driver and monitor for re-use
• Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
• Implement a collection of testcases each targeting a corner case of interest
• Create an abstraction of DUT registers and manage these registers during test
  

另外还有：
SystemVerilog Verification UVM 1.1 Student & Lab Guide 2011.12（可搜寻 PDF）
SystemVerilog Testbench Student & Lab Guide 2011.12（可搜寻 PDF）
Design Compiler 1 Student & Lab Guide 2012.06 （可搜寻 PDF）
IC Compiler 1 Student & Lab Guide 2010.12 （可搜寻 PDF）
IC Compiler 2 CTS Student & Lab Guide 2010.03 （可搜寻 PDF）