可实现高降压比的三种紧凑型解决方案

Olivier Guillemant，核心应用工程师

Question:
问题：
What are some methods for achieving a compact design under high step-down voltage ratios?

在高降压比下实现紧凑设计的方法有哪些？

Answer:
答案：
This article will address why the nonisolated DC-to-DC buck converter (referred to simply as buck converter in this article) is facing serious challenges to downconverting high DC input voltages to very low output voltages at high output current. Three different approaches will be presented for downconverting steep voltage ratios while keeping a small form factor.

本文将阐述为何非隔离式DC-DC降压转换器（在本文中简称为降压转换器）在高输出电流下将高DC输入电压转换为很低的输出电压时会面临严峻挑战。本文将介绍可以实现高降压比，同时保持小尺寸的三种不同方法。

Introduction
简介
System designers can be faced with the challenge of downconverting high DC input voltages to very low output voltages at high output current (such as 60 V down to 3.3 V at 3.5 A), while maintaining high efficiency, small form factor, and simple design.

系统设计人员可能会面临以下挑战：在高输出电流下将高DC输入电压下变频为极低输出电压（例如在3.5 A时从60 V降至3.3 V），同时保持系统的高效率、小尺寸并实现简单设计。

Combining high input-to-output voltage difference with high current automatically excludes the linear regulator due to the excessive power dissipation. Consequently, the designer must opt for a switching topology under these conditions. However, even with such topologies, it is still challenging to implement a design that is sufficiently compact for space-restricted applications.
将高输入-输出电压差值与高电流结合使用，会因为功耗过高自动将线性稳压器排除在外。因此，设计人员必须在这些条件下选择开关拓扑。但是，即使使用这种拓扑，对于空间有限的应用要实现足够紧凑的设计仍然相当困难。

Challenges Faced by DC-to-DC Buck Converters
DC-DC降压转换器面临的挑战
One candidate for high step-down ratios is the buck converter because it is the topology of choice when having to step down an input voltage to a lower output voltage (such as VIN = 12 V down to VOUT = 3.3 V) in an efficient way, with a significant amount of current while also using a small footprint. However, there are conditions under which the buck converter faces serious challenges to keep its output voltage regulated. To understand these challenges, we must remember that the simplified duty cycle (D) of a buck converter operating in continuous conduction mode (CCM) is:

要实现高降压比，一种方案是使用降压转换器，因为它是将输入电压高效降至更低的输出电压（例如，VIN = 12 V降至VOUT = 3.3 V）、仍然具有大量电流，且保持小尺寸的一种拓扑选项。但是，在某些情况下，降压转换器要保持输出电压稳定，会面临严峻的挑战。为了理解这些挑战，我们需要记住，在连续导通模式(CCM)下工作的降压转换器的占空比(D)可简化为：

Now, the duty cycle also relates to the switching frequency (fSW) in the following way, where the on-time (tON) is the duration over which the control FET stays on during each switching period (T):

占空比和开关频率(fSW)的关系如下所示，其中导通时间(tON)是指在每次开关期间(T)，控制FET保持开启的时长：

Combining Equation 1 and Equation 2 shows how tON is influenced by the step-down voltage ratio and fSW:

结合公式1和公式2可以看出，tON如何受降压比和fSW的影响：

Equation 3 tells us that the on-time decreases when the input-to-output voltage ratio (VIN/VOUT) and/or fSW increase. This means that the buck converter must be able to operate with very low on-time to regulate the output voltage in CCM under high VIN/VOUT ratio, and it becomes even more challenging with a high fSW.

从公式3可以看出，当输入-输出电压比(VIN/VOUT)和/或fSW增大时，导通时间会降低。这意味着降压转换器必须能够以很低的导通时间运行，以便在高VIN/VOUT比率下调节CCM中的输出电压，而在高fSW下这会更难实现。

Let’s consider an application with VIN(MAX) = 60 V, VOUT = 3.3 V at IOUT(MAX) = 3.5 A. When required, we shall use values from the LT8641 data sheet because a solution with the LT8641 will be provided in a later section. The required minimum on-time (tON(MIN)) corresponds to the highest input voltage (VIN(MAX)). In order to assess this tON(MIN), it is advised to make Equation 3 more accurate. By including VSW(BOT) and VSW(TOP), the voltage drops for the two power MOSFETs of the buck converter, and replacing VIN with VIN(MAX) we obtain:

我们假设在一个应用中，VIN(MAX) = 60 V，VOUT = 3.3 V，IOUT(MAX) = 3.5 A。在必要时，我们需要使用LT8641数据手册中的数值，因为在之后的章节中，我们将提供采用LT8641的解决方案。所需的最小导通时间(tON(MIN))对应最高输入电压(VIN(MAX))。为了评估这个tON(MIN)，建议提高公式3的准确度。通过包含降压转换器的两个功率MOSFET的压降VSW(BOT)和VSW(TOP)，并用VIN(MAX)替代VIN，我们得出：

Using Equation 4 with VIN(MAX), fSW = 1 MHz, we obtain a tON(MIN) of 61 ns. For VSW(BOT) and VSW(TOP), we made use of the values provided for RDS(ON)(BOT) and RDS(ON)(TOP) in the LT8641 data sheet, knowing as well that VSW(BOT) = RDS(ON)(BOT) × IOUT(MAX) and VSW(TOP) = RDS(ON)(TOP) × IOUT(MAX).

通过在公式4中使用VIN(MAX)、fSW = 1 MHz，我们得出tON(MIN)为61 ns。为了计算VSW(BOT)和VSW(TOP)，我们使用了LT8641数据手册中提供的RDS(ON)(BOT)和RDS(ON)(TOP)值，且已知VSW(BOT) = RDS(ON)(BOT) × IOUT(MAX)，VSW(TOP) = RDS(ON)(TOP) × IOUT(MAX)。

Buck converters can rarely guarantee a tON(MIN) with the short value of 61 ns obtained above; therefore, the system designer is forced to search for alternative topologies. There are three possible solutions for high step-down voltage ratios.

从上述公式可得到61 ns的数值，这样短的时间数值，降压转换器很难保证tON(MIN)；所以，系统设计人员不得不寻找可替代的拓扑。目前提供三种可实现高降压比的可行解决方案。

Three Compact Solutions for VIN(MAX) = 60 V, VOUT = 3.3 V at IOUT(MAX) = 3.5 A

三种紧凑型解决方案，VIN(MAX) = 60 V，VOUT = 3.3 V，IOUT(MAX) = 3.5 A

Solution 1: Using the LT3748 Non-opto Flyback
解决方案1：使用LT3748非光耦反激式变压器
The first option consists of using an isolated topology, where the transformer performs most of the downconversion thanks to its N:1 turn ratio. For that matter, Analog Devices offers flyback controllers such as the LT3748 that do not require a third transformer winding or opto-isolator, making the design simpler and compact. The LT3748 solution for our conditions is presented in Figure 1.

第一种选择是使用隔离拓扑，变压器具有N:1匝数比，负责执行大部分下变频。为此，ADI公司提供反激式控制器，例如LT3748，该控制器不需要第三个变压器绕组或光隔离器，使设计更简单，更紧凑。图1显示适用于这种情况的LT3748解决方案。

Even though the LT3748 solution simplifies the design and saves space compared with a standard flyback design, a transformer is still required. For applications where isolation between input and output sides is not required, it is preferred to avoid this component, which adds complexity and increases the form factor vs. a nonisolated solution.

尽管与标准反激式设计相比，LT3748解决方案简化了设计并节省了空间，但仍然需要使用变压器。对于无需隔离输入端和输出端的应用，最好是避免使用该组件，相比非隔离解决方案，该组件会增加设计复杂性和增大尺寸。

Solution 2: Using the LTM8073 and LTM4624 µModule Devices
解决方案2：使用LTM8073和LTM4624 µModule器件
As an alternative, the designer can downconvert in two steps. To achieve a reduced component count of only 10, two µModule® devices and eight external components can be used, as demonstrated in Figure 2. Moreover, the two µModule devices already integrate their respective power inductor, sparing the system engineer a design task that is rarely straightforward. The LTM8073 and LTM4624 both come in BGA packages, with respective dimensions of 9 mm × 6.25 mm × 3.32 mm and 6.25 mm × 6.25 mm × 5.01 mm (L × W × H), providing a solution with a small form factor.

作为一种替代方案，设计人员可以通过两个步骤进行下变频。要实现更少的组件数量（仅为10个），可以使用2个µModule®器件和8个外部组件，如图2所示。此外，这两款µModule器件已集成各自的功率电感，为系统工程师免除了一项困难的设计任务。LTM8073和LTM4624均采用BGA封装，尺寸分别为9 mm × 6.25 mm × 3.32 mm和6.25 mm × 6.25 mm × 5.01 mm (L × W × H)，可提供小尺寸解决方案。

Since the LTM4624 exhibits an efficiency of 89% under these conditions, the LTM8073 supplies at most 1.1 A to the input of the LTM4624. Given that the LTM8073 can provide up to 3 A of output current, it can be used to supply other circuit rails. It is with this purpose in mind that we selected 12 V as the intermediary voltage (VINT) in Figure 2.

由于在这些条件下LTM4624展现的效率为89%，LTM8073最多为LTM4624的输入端提供1.1 A。由于LTM8073可以提供高达3 A输出电流，因此可用来为其他电源轨供电。为此，在图2中，我们选择12 V作为中间电压(VINT)。

Despite avoiding the usage of a transformer, some designers might be reluctant to implement a solution that requires two separate buck converters, especially if no intermediary voltage is required to supply other rails.

尽管应避免使用变压器，但有些设计人员可能不愿使用需要两个独立的降压转换器的解决方案，尤其是无需采用中间电压为其他电源轨供电的情况下。

Solution 3: Using the LT8641 Buck Converter
解决方案3：使用LT8641降压转换器
Consequently, in many cases, using a single buck converter would be preferred because it provides the optimal solution to combine system efficiency, a small footprint, and design simplicity. But did we not just demonstrate that buck converters cannot cope with high VIN/VOUT combined with high fSW?

所以，在许多情况下，使用单个降压转换器成为首选，因为它是比较理想的解决方案，具有系统效率高、小尺寸和设计简单的特点。但是，我们前面不是展示降压转换器无法应对高VIN/VOUT和高fSW吗？

This statement might apply to most buck converters, but not to all of them. The ADI portfolio includes buck converters such as the LT8641, which is specified with a very short minimum on-time of 35 ns typical (50 ns max) over the full operating temperature range. Those specifications are safely below the required minimum on-time of 61 ns previously calculated, providing us with a third possible compact solution. Figure 3 shows how simple the LT8641 circuit can be.

这个说法可能适用于大部分降压转换器，但并非全部。ADI产品系列中包含LT8641之类降压转换器，在整个工作温度范围内，它具有较短的最低导通时间，一般为35 ns（最大50 ns）。这些规格都在之前计算得出的61 ns最小导通时间以下，为我们提供了第3种可行的紧凑型解决方案。图3显示LT8641电路有多么简单。

It is also worth noting that the LT8641 solution can be the most efficient of the three. Indeed, if efficiency must be further optimized compared with Figure 3, we can decrease fSW and select a bigger inductor size.

还有一点值得注意，LT8641解决方案可能是3种解决方案中最高效的。事实上，如果与图3相比必须进一步优化效率，我们可以降低fSW并选择更大的电感尺寸。

Although fSW can also be decreased with Solution 2, the integration of the power inductors does not offer the flexibility to increase the efficiency beyond a certain point. Moreover, the use of two consecutive downconversion stages has a small negative impact on the efficiency.

尽管也可以通过解决方案2来降低fSW，但集成功率电感后无法灵活提高效率，达到高于某个点的目标。此外，使用两个连续下变频级对效率的负面影响较小。

In the case of Solution 1, the efficiency will be very high for a flyback design, thanks to the operation in boundary mode and to all components removed with the no-optical feedback design. However, the efficiency cannot be fully optimized because there is a limited number of transformers to select from, as opposed to the broad portfolio of inductors available for Solution 3.

在使用解决方案1时，由于在边界模式下运行，以及在非光学反馈设计中移除了所有组件，因此反激式设计的效率非常高。但是，效率不能完全优化，因为可选的变压器数量有限，而解决方案3则有广泛的电感产品系列可供选择。

Figure 1. A circuit solution with the LT3748 downconverting 60 V input to 3.3 V output.
图1.采用LT3748的电路解决方案，将60 V输入下变频至3.3 V输出。

Figure 2. A circuit solution with the LTM8073 and LTM4624, downconverting 60 V input to 3.3 V output.
图2.采用LTM8073和LTM4624的电路解决方案，将60 V输入下变频至3.3 V输出。

Figure 3. A circuit solution with the LT8641 downconverting 60 V input to 3.3 V output.
图3.采用LT8641的电路解决方案，将60 V输入下变频至3.3 V输出。

An Alternative Way to Check Whether LT8641 Fulfills Requirements
检查LT8641是否满足要求的另一种方法
In most applications, the only adjustable parameter in Equation 4 is the switching frequency. Consequently, we reformulate Equation 4 to assess the maximum permitted fSW for the LT8641 under given conditions. By doing this, we obtain Equation 5, which is also provided on page 16 of the LT8641 data sheet.

在大多数应用中，公式4中唯一可调的参数是开关频率。因此，我们重新变换公式4，以评估LT8641在给定条件下允许的最大fSW。于是，我们得到公式5，LT8641数据手册的第16页也提供了这个公式。

Let’s use this equation with the following example: VIN = 48 V, VOUT = 3.3 V, IOUT(MAX) = 1.5 A, fSW = 2 MHz. An input voltage of 48 V is commonly found in automotive and industrial applications. By inserting those conditions in Equation 5, we obtain:

我们在以下示例中使用此公式：VIN = 48 V，VOUT = 3.3 V，IOUT(MAX) = 1.5 A，fSW = 2 MHz。汽车和工业应用中经常使用48 V输入电压。在公式5中代入这些条件后，我们得出：

Therefore, under the provided application conditions, the LT8641 would operate safely with fSW set as high as 2.12 MHz, confirming that the LT8641 is a good choice for this application.

因此，在给定的应用条件下，在fSW高达2.12 MHz时，LT8641能够安全运行，证实LT8641是适合此应用的一个不错的选择。

Conclusion
结论
Three different methods were presented to achieve a compact design under high step-down voltage ratios. The LT3748 flyback solution does not require a bulky opto-isolator and is recommended for designs where isolation is necessary between input and output sides. The second method, which involves implementing the LTM8073 and LTM4624 µModule devices, is of particular interest when the designer is hesitant to select the optimal inductor for the application and/or when an additional intermediary rail must be supplied. The third method, a design based on the LT8641 buck converter, offers the most compact and simplest solution when the sole requirement is the steep voltage downconversion.

本文提出了三种不同的方法，以在高降压比下实现紧凑型设计。LT3748反激式解决方案不需要使用笨重的光隔离器，推荐用于需要隔离输入端和输出端的设计。第2种方法需要使用LTM8073和LTM4624 µModule器件，当设计人员为应用选择最佳电感犹豫不决，以及/或何时必须提供额外的中间电源轨时，这种解决方案会非常有用。第3种方法基于LT8641降压转换器进行设计，如果只是要求实现陡电压下变频时，可提供紧凑且简单的解决方案。

About the Author
作者简介
Olivier Guillemant is a central applications engineer at Analog Devices in Munich, Germany. He provides design support for the Power by Linear portfolio for European broad market customers. He has held various power application positions since 2000 and joined ADI in 2021. He received his M.Sc. in electronics and telecommunications from University of Lille, France.

Olivier Guillemant是ADI公司的核心应用工程师，工作地点在德国慕尼黑。他为欧洲的广泛市场客户提供Power by Linear产品组合的设计支持。他自2000年起担任过各种电源应用职位，于2021年加入ADI公司，拥有法国里尔大学的电子和电信硕士学位。