GD32系列MCU芯片内部结构拆解与Flash代码数据读写注意点

mars4zhu

战斗民族俄罗斯的芯片拆解团队Zeptobars拆开的GD32F103的MCU

https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices

采用的串行Flash映射到芯片内部的SRAM作为代码运行，因此GD32的MCU实现所谓的Flash零等待，跑到200MHz。

但是前部分的Flash访问速度特别快，但是后半部分的会特别慢。





GD32F103CBT6 - Cortex-M3 with serial flash : weekend die-shotGiga Devices GD32F103CBT6 really surprised us:



Giga Devices was a serial flash manufacturer for quite some time. When they launched their ARM Cortex M3 lineup (with some level of binary compatibility to STM32) - instead of going conventional route of making numerous dies with different flash and SRAM sizes they went for SRAM&logic die and separate serial flash die. How this could work fast enough? Keep reading :-) At least ESP8266 already taught us that executing code from serial flash and reaching acceptable speed is not impossible.

Use of serial flash allows Giga Devices to increase maximum flash size in their microcontrollers quite a bit (currently they have up to 3MiB) and to save quite a bit on ARM licensing fees (if they are paying "per die design").


Die has 110 pads, 9 of which are used by a flash die. GD32F103CBT6 is in TQFP48 package - which again suggests that this die is universal and also used in higher pin count models. Die size 2889x3039 µm.

Logo:


ADC capacitor bank:


After etching to poly level we clearly see that there is no flash on the die:


SRAM sizes are 32KiB in each largest block (128 KiB total) - stores code, which means first 128KiB could be accessed faster than typical flash. GD32 chips with 20Kb of SRAM or less have no more than 128KiB of flash, so all flash content is served from SRAM. This might also mean that startup time is slower than one would expect. With this SRAM mirroring it is not surprising that GD32 is beating STM32 in performance even on the same frequency and loosing in idle & sleep power consumption. Consumption at full load is lower than STM32 due to better (smaller) manufacturing technology.

2 smaller blocks are 10KiB each and are likely to be user-accessible SRAM.
4 smallest blocks closest to the synthesized logic are 512B each.

SRAM has cell size 2.04 µm², which is ~110nm. Scale 1px = 57nm:


Standard cells:


Low power standard cells:


Flash die:

Flash die size: 1565x1378 µm.

PS. Thanks for the chips go to dongs from irc.

stary666

这是国产芯片，不是战斗民族的

mars4zhu

stary666 发表于 2017-5-3 11:25
这是国产芯片，不是战斗民族的

战斗民族拆解了，暴力强酸溶解

stary666

哦，这样的啊，，，，