FSL bus IP core and its MicoBlaze System

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Abstract MicroBlaze company is based on a new generation of FPGA devices Xilinx soft processor core. The FSL bus is the FIFO one-way links, can be user-defined IP core and MicroBlaze internal high-speed general-purpose register direct. In this paper, several major MicroBlaze bus interface summary comparison of a detailed analysis on the structure of FSL bus, features, working principle and configuration methods. Vector reduction through anapplication of Chinese characters, the specific description of the FPGA system-on-chip design to integrate the use of FSL high-speed bus IP core user-defined, soft-processor system to achieve hardware-accelerated methods and steps.

Key words FPGA IP core soft-core processor FSL bus MicroBlage

Introduction

With the development of semiconductor manufacturing technology to FPGA (field programmable gate array) to represent a new generation of programmable logic device (PLD) of the increasing density of logic resources, making programmable technology naturally with the system chip integration technology (SoC) integration of the increasingly close and has gradually become a platform technology can be configured (configurable platform) of the mainstream.

At present, the major pld vendor FPGA-based configurable platform although most of the "programmable logic microprocessor 10" framework, but in the development of FPGA-based embedded systems, has adopted a different approach to integration of processor system and other on-chip logic resources (the majority of users in the form of IP core). MicroBlaze soft-core processor is the FPGA device Xilinx for its development, its unique FSL (Fast Simplex Link, fast one-way link) bus, a user IP core can be achieved with the soft-core processors, high-speed connectivity for designers provides a means of solving such problems.

1 MicroBlaze soft-core processor

1.1 Overview

Xilinx Inc. MicroBlaze is a FPGA-based soft microprocessor IP core. It uses the Harvard RISC architecture and the structure of the 32-bit instruction and data bus, there are 32 general-purpose 32-bit width register; in the 150 MHz clock frequency, up to 125 DMIPS of processing performance, and its logical structure in Figure 1 (Figure omitted from the side of the same command interface). Xilinx offers the use of the EDK (Embedded System Development Kit), can be parameterized graphical interface to facilitate completion of the embedded soft-processor system design. Its outstanding advantages, first, design flexibility; The second is to integrate user-defined IP core, the algorithm can be implemented in parallel hardware rather than software serial implementation, which greatly accelerated the pace of implementation of the software, the so-called hardware acceleration.

1.2 MicroBlaze soft-core bus interface

MicroBlaze soft processor core with a rich interface resources. At present, the latest version of the MicroBlaze soft-core support for the interface standard are:

◆ bytes allowed with OPB (On-chip Peripheral Bus, on-chip peripheral bus) V2.0 interface;

◆ High-speed LMB (Local Memory Bus, the local memory bus) interface;

◆ FSL master and slave device interface;

◆ XCL (Xilinx Cache Link, Xilinx cache link) interface;

◆ with MDM (Microprocessor Debug Module) interface to connect the debugger.

OPB on-chip IBM Core Connect bus standard part of the realization for the IP core as a peripheral to connect to the MicroBlaze system. LMB to achieve on-chip high-speed access to the blockRAM. MicroBlaze soft-core FSL is a unique one-way based on the FIFO links, can be user-defined nuclear and MicroBlaze internal IP registers directly connected to GM; and XCL is the MicroBlaze soft-core new for the realization of the memory chip high-speed access. MicroBlaze soft-core there is a dedicated debug interface, through parameter setting, developers can use only the required application-specific processor features.

1.3 MicroBIaze system hardware acceleration

Nuclear integration of user IP-based embedded MicroBlaze soft-core processor systems, usually have two methods: one method is to connect to the IP core OPB bus; The second method is to user-specific IP to connect to the MicroBlaze FSL bus. OPB and the FSL compared as listed in Table 1.

Note: ① Data FSL_v20 from opb_v20 and manual data;

② the data bus configuration in the main 2 for 1 from the circumstances;

③ the data in terms of the MicroBlaze soft-core.

Can be seen from Table 1, despite the OPB and the FSL are MicroBlaze soft-core chip with the FPGA logic resources for other main way to connect, but its characteristics are different from the division of labor: OPB bus will be applied to low-speed and low-performance requirements of the equipment connected to the MicroBlaze system; and FSL bus is applicable to the time requirements of the user-defined IP core into a MicroBlaze soft-core-based system, in order to achieve hardware acceleration.

2 FSL Bus

2.1 FSL Bus Interface

FSL bus is a one-way FIFO-based point-to-point communication bus, mainly for two FPGA modules asked for quick communication. FSL bus IP core structure as shown in Figure 2, FSL interface the I / O signals as listed in Table 2.

The main features of the interface:

◆ unidirectional point-to-point communication;

◆ Non-shared communication mechanism without arbitration;

◆ support the control of the separation of digital and data communications;

◆ FIFO-based communication mode;

◆ configurable data width;

◆ High-speed communication performance (stand-alone reached 600 MHz).

2.2 FSL Bus Write Timing

On the FSL bus write operation is controlled by the signal FSL_M_Write. Figure 3 is the FSL bus timing of the write operation. FSL master clock rising edge in the first inspection did not signal the FSL_M_Full high, on the main equipment will be allowed to purchase high-FSL_M_Write and onto the bus FSL_M_Data and FSL_M_Control the next clock cycle the data bus to be read and sent to into the FIFO. Map Write2 and Write3 is a set of "back-to-back" for the write operation. In Write3 when, FIFO full signal is home made FSL_M_Full high, forcing the cancellation of their main equipment FSL_M_Write signal, until the first read operation will be low FSL_M_Full home, we can write operation initiated by another. Therefore, the figure implies that also occurred in Write4 a read operation from the equipment, or high FSL_M_Full will once again home.

2.3 FSL Bus Read Timing

Reading of the FSL bus operation is controlled by the FSL_S_Read signal, Figure 4 is the FSL equipment 3 times from the time the operation timing. FSL bus when there is valid data (FSL_S_Exists ='1 '), FSL_M_Data the data and control bit FSL_M_Control immediately FSL can be read from the device. Once complete the read operation from the device, FSL_S_Read signal must buy a high one clock cycle, from the equipment to confirm the successful completion of a read operation. After the read operation in the clock rising edge (figure Read2 Department), FSL_M_Data and FSL_M_Control will be updated as new data, at the same time FSL_M_Full signal FSL_S_Exists and will be updated. Similarly, here, implies that Readl and Read2 in between two write operations of the main equipment.

3 FSL bus usage

3.1 the use of FSL bus IP core communication equipment

Xilinx is currently provided by FSL bus IP core version FSL_V20. FSL two devices to be used for data transmission, it is necessary to separate from the main equipment or equipment connected to the FSL core. If you need two-way transmission, as long as the two devices as master and slave devices, respectively, the use of two nuclear connection FSL.

Either as the main equipment or from equipment, will require the adoption of the microprocessor in the device description file peripherals (MPD) in the corresponding definition in order to achieve the required types of FSL interface. The following code is a definition of the FSL, respectively, the main device interface from the device interface FSL_OUT and FSL_IN the MPD documents:

BEGIN my_fsl_peripheral

OPTl0N IPTYPE = PERIPHERAL

OPTl0N IMP_NETLIST = TRUE

BUS_INTERFACE BUS = FSL_IN, BUS_STD = FSL, BUS TYPE = SLAVE

BUS_INTERFACE BUS = FSL_OUT, BUS_STD = FSL, BUS_TYPE = MASTER

# # Ports

PORT CLK = "", DIR = IN, SIGIS = CLK

PORT RESET = "". DIR = IN

PORT FSL_S_READ = FSL_S_Read, DIR = out, BUS = FSL_IN

PORT FSL_S_DATA = FSL_S_Data, DIR = in, VEC = [o: 31], BUS = FSL_IN

PORT FSL_S_CONTROL = FSL_S_Control, DIR = in, BUS = FSL_IN

PORT FSL_s_EXISTS = FSL_S_Exists, DIR = in, BUS = FSL_IN

PORT FSL_M_WRITE = FSL_M_Write, DIR = out, BUS = FSL_OUT

PORT FSL_M_DATA = FSL_M_Data, DIR = out, VEC = [o: 31], BUS = FSL_OUT

PORT FSL_M_CONTROL = FSL_M_Control, DIR = out, BUS = FSL_OUT

PORT FSL_M_FULL = FSL_M_Full, DIR = in, BUS = FSL_OUT

3.2 Communication through the FSL with the MicroBlaze

MicroBlaze soft-core support of the FSL bus interface to connect up to eight pairs of FSL, the specific realization of the number of interface description files from the system hardware (MHS) parameters C_FSL_LINKS decision. By default the parameter is 0, indicated that he did not achieve the FSL interface. FSL bus when the need to use the MicroBlaze and the FPGA in one or more logic modules connect, it is important to set the value of the parameter number for the corresponding module. This parameter range is 0 ~ 8.

MicroBlaze instructions are concentrated in the FSL bus for the operation of instructions, they are:

◆ get, put - read and write data blocking FSL, control signals are set to 0;

◆ nget, nput - data read and write non-blocking FSL, control signals are set to 0;

◆ cget, cput - control-bit read-write blocking FSL, control signals are set to 1;

◆ ncget, ncput - control-bit read and write non-blocking FSL, control signals are set to 1.

application 4 FSL Bus

In the following example, try to FSL bus technology, to achieve a specific function of the user-defined function IP core integrated into the MicroBlaze soft-core system, in order to achieve the purpose of hardware acceleration. Here a character vector (vector font) to restore the function of the integration of hardware modules as an example to show the application of the process of FSL bus. Development platform used by Memec Insight is produced by the Virtex-II series MicroBlaze development board, on-board FPGA device used for the Virtex-II 1000, the system clock to 100 MHz, Development Tools for Xilinx's EDK 6.3 and ISE 6.3.

4.1 FSL bus applications

Figure 5 shows, vectOr_font nuclear FSL_Lattice through FSL_Code-2 and FSL bus and directly connected to MicroBlaze soft-core.

For FSL_Code bus, MicroBlaze core is the main equipment, and equipment from nuclear vector_font. This can MicroBlaze bus FSL_Code nuclear vectOr_font send characters to the area code (or other character encoding formats, by using the vector font and restore the decision algorithm), as well as attribute information of Chinese characters (such as font, size, etc.).

FSL_Lattice bus for just the opposite. nuclear vector font as the main device can send it to the MicroBlaze core after reduction treatment, the Chinese character dot-matrix dot-matrix data, as well as the size information (for the lattice data in memory in the show organized into the correct format).

4.2 data transfer command and control application-bit instructions

FSL provides independent control of data transmission can be used for digital transmission of data is tagged. In order to district character code data and attribute data, as well as the Chinese character dot-matrix dot-matrix data and data size. FSL of MicroBlaze through command and control data-bit transfer instruction to send the area code of Chinese characters and Chinese characters attribute information, receiving Chinese character dot-matrix dot-matrix data and size information. The realization of the corresponding code is as follows:

/ / Use non-blocking data write function to write characters to the FSL bus location code Microblaze_nbwrite_datatsl (code, O)

/ / Use non-blocking function of the control bit to write Chinese characters to write to the FSL bus attribute information maicroblaze_cnbwrite_cnlfsl (attibute, O)

/ / Use non-blocking function of the data read from the FSL data bus to read dot matrix characters microblaze_nbread_datafsl (1attice , O)

/ / Use non-blocking function of the control bit from the FSL bus time to read Chinese characters dot size information microblaze_cnbread_cnlfsl (size, O)

Code used with the FSL of the function definition, are under the include directory mb_interface. h file. Among them, the function's second parameter to read and write operations on behalf of the FSL bus interface number, the corresponding Mi-croBlaze of eight pairs of soft-core FSL interface. The parameter values range from 0-7. In this case, MicroBlaze using only a pair of FSL interfaces, therefore a value of 0.

4.3 to achieve the steps

First of all, in the Base System Wizard is designed as shown in Figure 5 the dashed border in a simple system of the MicroBlaze embedded processor. Then, in the XPS complete integrated development environment user-defined IP core (in this case that the nuclear vectoz__font) Add, Microblaze add nuclear FSL interface (setting parameters C_FSL_LINKS = 1), the addition of two FSL bus IP core, respectively, to achieve FSL_Code and FSL_Lattice bus. In addition, the two FSL bus IP core parameters C_USE_CONTROL home to 1 in order to open the FSL control-bit bus transfer. All of these changes, the final will be updated to the MES file. In this way, the hardware platform can platgen generation tool based on its need to generate FPGA configuration file.

Upon completion of the realization of hardware, software parameters for the corresponding settings, such as the system point to the standard input and output devices such as UART modules. Then, a tool used to generate libraries libgen, in accordance with MSS (System Software Description File) file, the peripheral functions required for the header files added to project.

By calling these functions, you can operate and control these peripherals. Tool-ri through the build order, call the mb-gcc: Compiler tools, applications will be prepared compiled ELF files, and then order updatebitstrcam code to initialize the corresponding data RAM is added to the previous generation of FPGA configuration file, bit to generate the final profile. Finally, the use of bit file download command will download to the target board.

FSL over the entire application process designed to achieve. In order to illustrate this example is the use of FSL bus. Practical applications can also be adopted in accordance with the specific circumstances of FSL, to be more user-defined IP core (such as DCT, FFT, etc.) added to the. MicroBlaze soft-core system.

Conclusion

In the development of embedded systems, people have always hoped to have a need to meet their own "custom" of the embedded processor, rather than on-hand and there are a lot of common microprocessors. However, directly to the user-defined IP core added to the processor core, the processor not only by the shackles of the original structure, but also may reduce the performance of the processor (processor frequency); and with the internal register is directly connected to the FSL interface , user-defined IP processors can damage the original structure, closely with MicroB-laze combination of soft-core. In this way, even if the critical path coverage of the user IP core, as its core processor, the processor will not result in lower clock frequency.

FSL bus through analysis and verification of the above examples demonstrated that in the field of SoC based on the MicroBlaze system design, on the one hand, specific applications can be "tailored" approach to design; On the other hand, to use its dedicated FSL bus interface technology, the realization of embedded soft-processor system with the user-defined logic of integration, in order to improve the system frequency is not the premise, through some function of the hardware features to improve system performance.