CMOS锁相环合成器-分析与设计

caroline11

本书介绍了锁相环合成器设计和分析技术的基本原理和现状。本书涵盖了系统级和电路级设计和分析的完整概述。在0.35m m CMOS中实现了一个16mW, 2.4GHz, sub-2V, Sigma Delta分数n合成器原型。它具有高速、稳健的相位开关预缩放器和低复杂度、高效面积的环电容乘法器，很好地解决了锁相环合成器的速度和集成瓶颈。这本书被认为是学术界研究人员和工业设计工程师必读的锁相环合成器手册。
This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly.
This book is conceived as a PLL synthesizer manual for both academia researchers and industry design engineers.