ESD保护电路的特性、建模及设计

caroline11

For more than 20 years, susceptibility of integrated circuits to electrostatic discharge (ESD) has warranted the use of dedicated on-chip ESD protection circuits. Although the problem of ESD in integrated circuits (ICs) has received much attention industry-wide
since the late 1970s, design of robust ESD circuits remains challenging because ESD failure mechanisms become more acute as critical circuit dimensions continue to shrink. In the past increased sensitivity of smaller devices, coupled with a lack of understanding
of ESD phenomena and the consequent trial-and-error approach to ESD circuit design, resulted in design of ESD protection effectively starting from scratch in each new technology. Now, as life cycles of new technologies continue to decrease, better analysis capabilities and a systematic design approach are essential to accomplishing the increasingly difficult task of adequate ESD protection-circuit design。