The proliferation of a multitude of wireless standards as well as the interest in cognitive radios have resulted in the need for a highly reconfigurable radio-frequency (RF) receivers. Reconfigurability in an RF receiver has to be obtained with a negligible degradation in circuit performance, power consumption and silicon area. Digital signal processing offers a degree of flexibility that is perhaps unmatched by analog circuits. Nevertheless, a strategy of processing an RF signal entirely in the digital domain would place an incredible burden in the analog-to-digital converter circuits.