CMOS SRAM设计

caroline11

The process technology scaling and push for better performance enabled embedding of millions of Static Random Access Memories (SRAM) cells into contemporary ICs. In several applications, the embedded SRAMs can occupy the majority of the chip area and contain hundreds of millions of transistors. As the process technology continues to scale deeper into the nanometer region, the stability of embedded
SRAM cells is a growing concern. As a consequence, large SRAM arrays impact all aspects of chip design and manufacturing because they became the yield-limiters in modern high-performance ICs. However, the robust detection of SRAM cells with marginal stability is a non-trivial task. While the traditional march tests are unable to detect unstable cells, the conventional data retention tests that are intended to expose marginal cells have unacceptable sensitivity and are uneconomical due to the long test time and high-temperature requirements. These factors show the growing disparity between the traditional SRAM test practices and the need for an economical SRAM cell stability tests that can help to achieve lower defect counts in the shipped parts. While various aspects of SRAM design and test have been addressed in special literature, no cohesive text provides a systematic overview of SRAM cell stability and the specialized design and test approaches it requires.