ESD in layout

caroline11

Abstract --- This paper presents a high ESD performance NPN protection structure for advanced submicron BiCMOS and Bipolar processes. Using a zener trigger circuit and a specific multi-emitter layout technique, this paper successfully demonstrates an optimal protection structure to meet the requirements imposed on advanced submicron circuit applications. The protection circuit has a low trigger voltage as well as a low capacitance load and does not add any series resistance.