高速IO用ESD二极管的本征特性研究

caroline11

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degrada-tion on circuit performance, especially in the high-speed I/O applications. In this work, two modified lay-out styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (RONCESD, ICP/CESD, VHBM/CESD, and ICP/ALayout) of ESD protection diodes with new proposed layout styles can be successfully improved.

为了满足静电放电(ESD)的鲁棒性，在集成电路(ic)的I/O单元中加入了ESD二极管。然而，ESD二极管的寄生电容往往会导致电路性能下降，特别是在高速I/O应用中。本文提出了两种有效提高静电放电保护二极管性能的改进布局样式，即多华夫形布局样式和多华夫形空心布局样式。90纳米CMOS工艺的实验结果证实，采用新提出的布局样式的ESD保护二极管的FOMs (RONCESD、ICP/CESD、VHBM/CESD和ICP/ alout)可以成功改进。