CM0S高速光互连收发器的设计

caroline11

The increase in computing power enabled by CMOS scaling has created increased demand for chip-to-chip I/O bandwidth. Unfortunately, inter-chip electrical channel bandwidth has not scaled similarly to on-chip performance, causing current high-speed I/O link designs to be channel limited and require sophisticated equalization circuitry which increases power consumption. Interconnect architectures which employ optical channels have negligible frequency dependent loss and provide a potential path to increased I/O bandwidth without excessive circuit complexity or power consumption.
CMOS扩展所带来的计算能力的提高，增加了对芯片到芯片I/O带宽的需求。不幸的是，芯片间的电气通道带宽没有像芯片上的性能一样扩展，导致当前的高速I/O链路设计受到通道限制，需要复杂的均衡电路，这增加了功耗。采用光通道的互连架构具有可忽略的频率相关损耗，并在不增加电路复杂性或功耗的情况下提供了增加I/O带宽的潜在途径。