Design and Power Optimization of High-Speed

caroline11

This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications.Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5µm standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s

本文提出了一种适用于宽带CDMA应用的7位64 MS/s流水线a /D转换器。为了实现高速低功耗，采用了数字校正和电容值优化缩放等技术。采用开关opamp技术进一步降低功耗。该ADC采用0.5 μ m标准CMOS工艺实现。该ADC采用0.5 μ m标准CMOS工艺实现。