Study of intrinsic characteristics of ESD diodes for highspeed IO

caroline11

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degrada-tion on circuit performance, especially in the high-speed I/O applications. In this work, two modified lay-out styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (RONCESD, ICP/CESD, VHBM/CESD, and ICP/ALayout) of ESD protection diodes with new proposed layout styles can be successfully improved.