李宇根在清华讲授的pll课件

caroline11

I. Overview of Clocking and Frequency Generation
1. Course introduction
2. Phase-locked clocking in modern communication systems
II. Phase-Lock Basics
1. PLL linear model
2. Loop components
3. Loop dynamics
4. Transient response and acquisition
5. PLL behavioral simulations
III. PLL Design
1. System design perspectives
-spur and modulation
-phase noise/jitter
-settling time
-bandwidth optimization
2. Circuit design aspects
-phase detector
-charge pump
-frequency divider
-voltage-controlled oscillator
3. Delay-locked loop
IV. Applications
1. Frequency synthesizers for RF applications
-system design consideration; phase noise, spur, and settling time
-integer-N/fractional-N frequency synthesizers
-direct digital frequency synthesizer
2. Clock-and-data recovery for serial link and optical communications
-system design considerations; jitter transfer, jitter tolerance, and jitter generation
-circuit design aspects in multi-Gb/s SerDes systems
-DLL-based CDR for serial-link backplane applications
-D/PLL-based CDR for SONET applications
3. Clock multiplier unit for digital clock generation
-system design considerations; RJ, DJ, long-term jitter, and short-term jitter
-circuit design for high supply rejection
-examples; PLL design for FB-DRAM, multiplying DLL (MDLL) for low jitter accumulation
4. PLL for “design on demand”
V. Advanced Topics
1. Recent PLL works and trends
2. Coupling effects on PLL performance
3. Various in-situ calibration/compensation methods for technology-friendly PLL
4. Future challenges
VI. Project Discussion