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发表于 2021-11-24 13:21:01 | 显示全部楼层 |阅读模式
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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits
Economizing TSV Resources in 3-D Network-on-Chip Design

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

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