Fault-Tolerance Techniques for SRAM-based FPGAs

zhang1998

Fault tolerance on semiconductor devices has been a meaningful matter since upsets were first experienced in space applications several years ago. Since then, the interest in studying fault-tolerant techniques in order to keep integrated circuits (ICs) operational in such hostile environment has increased, driven by all possible applications of radiation tolerant circuits, such as space missions, satellites, high-energy physics experiments and others (Nasa, 2003). The development of fault-tolerant techniques is strongly associated with the target device, and it requires a detailed analysis of the effects of an upset on the related architecture. For each type of circuit, there is a set of most suitable solutions to be applied. In the past years, the integrated circuit industry has designed more and more complex architectures in order to improve performance, to increase logic density and to reduce cost. Examples of this development include Application Specific Integrated Circuits (asics), microprocessors composed of millions of transistors, highdensity Field Programmable Gate Array (FPGA) components and, more recently, System-on-a-Chip (SOC) composed of embedded microprocessors, memories and Analog blocks. These architectures have made a dramatic impact on the way systems are designed, providing a large amount of information processing on a single chip. They cover a wide range of applications, from portable systems to dedicated embedded control units and computers. In particular, FPGAs have made a major improvement in systems design by adding the reconfigurability feature, which reduces the time to market and increases the design flexibility.