完全可综合的SPI模块verilog代码

zhang1998

附件有详细的设计规格书。Features
- Compatible with Motorola's SPI specifications
- Enhanced Motorola MC68HC11 Serial Peripheral Interface
- 4 entries deep read fifo
- 4 entries deep write FIFO
- Interrupt generation after 1, 2, 3, or 4 transfered bytes
- 8 bit WISHBONE RevB.3 Classic interface
- Operates from a wide range of input clock frequencies
- Static synchronous design
- Fully synthesizable
- 130LUTs in a Spartan-II, 230 LCELLs in an ACEX