IC设计经典之作：digital system clocking

zhang1998

CONTENTS
Preface
Chapter 1 Introduction
1.1 Clocking in Synchronous Systems
1.2 System Clock Design
1.2.1 Global System Clock Generation
1.2.2 On-Chip Clock Generation
1.2.3
1.2.4 Design Considerations
1.3 Timing Parameters
1.3.1 Clock Skew
1.3.2 Clock Jitter
1.4 Clock Signal Distribution
1.4.1 Historical Overview
1.4.2
Noise Sources and Loop Bandwidth
Clock Distribution in Modern Microprocessors
Chapter 2 Theory of Clocked Storage Elements
2.1 Latch-Based Clocked Storage Elements
2.1.1 True-Single-Phase-Clock Latch
2.1.2 Pulse Register Single Latch
2.2.1 Time Window-Based Flip-Flops
2.2 Flip-Flop
Chapter 3 Timing and Energy Parameters
3.1 Timing Parameters
3.1.1 Clock-to-Output Delay, t c ~
3.1.2 Setup Time, U
3.1.3 Hold Time, H
3.1.4
3.1.5
3.1.6 Minimum Data Pulse Width
3.2.1 Components of Energy Consumption
3.2.2 Energy Breakdown
3.2.3 Energy per Transition
3.2.4 Glitching Energy
Interface with Clock Network and Combinational
Logic
3.3.1 Interface with Clock Network
3.3.2 Interface with Combinational Logic
Late Data Arrival and Time Borrowing
Early Data Arrival and Internal Race Immunity
3.2 Energy Parameters
3.3
Chapter 4 Pipelining and Timing Analysis
4.1 Analysis of a System that Uses a Flip-Flop
4.1.1 Late Data Arrival Analysis
4.1.2 Early Data Arrival Analysis
Analysis of a System that Uses a Single Latch
4.2.1 Late Data Arrival Analysis
4.2.2 Early Signal Arrival Analysis
Analysis of a System with a Two-Phase Clock
and Two Latches in an M-S Arrangement
Analysis of a System with a Single-Phase Clock
and Dual-Edge-Triggered Storage Elements
4.4.1 Late Data Arrival
4.4.2 Early Data Arrival
4.2
4.3
4.4
Chapter 5 High-Performance System Issues
5.1 Absorbing Clock Uncertainties
Clock Edge
Absorption
5.1.1 Clock-Uncertainty Absorption Using Soft
5.1.2 Timing Analysis with Clock-Uncertainty
5.1.3 Clock-Uncertainty Absorbing Considerations
5.2 Time Borrowing
5.2.1 Dynamic Time Borrowing
5.2.2 Static Time Borrowing
Time Borrowing and Clock Uncertainty
5.3.1 Level-Sensitive Clocking
5.3.2 Soft-Edge-Sensitive Clocking
5.3
Chapter 6 Low-Energy System Issues
6.1 Low-Swing Circuit Techniques
6.1.1 Conventional CSEs with Reduced-Swing Clock
Drivers
6.1.2 CSE Redesign
6.1.3 N-Only CSEs with Low-Supply-Operated Clock
Drivers
6.2 Clock Gating
6.2.1 Global Clock Gating
6.2.2 Local Clock Gating
6.3.1 Latch-Mux Design
6.3.2 Pulsed-Latch Design
6.3.4 Clock Distribution
6.3 Dual-Edge Triggering
6.3.3 Flip-Flop
6.4 Glitch Robust Design
Chapter 7 Simulation Techniques
The Method of Logical Effort
7.1.1 Multistage Logic Networks
7.1.2 Logical Effort of Logic Gates Commonly Found in
CSEs
7.1
7.2 Environment Setup
7.2.1 HLFF Sizing Example
7.2.2 M-SAW Sizing Example
7.2.3 Energy Measurements
7.2.4 Automating the Simulations
7.3 Appendix
7.3.1 The CSE Characterization Script
7.3.2
7.3.3
Simulation Bench for F04 Inverter Delay Extraction
(simInv.hsp)
CSE Simulation Bench in SPICE (sim.hsp)
7.3.4 Example HLFF Deck (hllfl6.hsp)
7.3.5 Example M-SAFF Deck (saff16.h~~)
Chapter 8 State-of-the-Art Clocked Storage Elements in
CMOS Technology
8.1 Master-Slave Latch Examples
8.1.1 Derivation of Master-Slave Latch
8. I .2
8.1.3 Comparison
8.2 Flip-Flop Examples
8.2.1 Hybrid-Latch Flip-Flop
8.2.2 Semidynamic Flip-Flop
8.2.3 Sense- Amplifier-B ased Flip-Flop
8.2.4 Modified Sense-Amplifier-Based Flip-Flop
8.2.5 Comparison
Clocked Storage Elements with Local Clock Gating
8.3.1
8.3.2 Data-Transition Look-Ahead Latch
8.3.3 Clock-on-Demand Pulsed Latch
8.3.4 Conditional Capture Flip-Flop
8.3.5 Comparison
8.4.1 CSE Examples
8.4.2 Comparison
8.5.1 DET Latch-Mux
8.5.2 DET C2MOS Latch-Mux
8.5.3 DET Pulsed-Latch
8.5.4 DET Symmetric Pulse Generator Flip-Flop
8.5.5 Comparison
8.6 Summary
C2MOS Master-Slave Latch
8.3
Master-Slave Latch with Local Clock Gating
8.4 Low-Swing Clock Storage Elements
8.5 Dual-Edgc-Triggered Clocked Storage Elements
Chapter 9 Microprocessor Examples
9.1 Clocking for Intel Microprocessors
9.1. I IA-32 Pentium Pro
9.1.2 First IA-64 Microprocessor
9.1.3 Pentium 4
9.2 Sun Microsystems Ultrasparc-I11 Clocking
9.2.1 Clocking
9.2.2 Storage Elements
CONTENTS Xi
9.3 Alpha Clocking: A Historical Overview
9.3.1 Clocking
9.3.2 Clocked Storage Elements
Clocked Storage Elements in IBM Processors
9.4.1 Level-Sensitive Scan Design
9.4.2
9.4
Examples of Clocked Storage Elements
References
Index 241