[ebook]Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

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Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC (System-on-Chip Design and Technologies) by Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi [size=120%]Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC (System-on-Chip Design and Technologies) By Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi Publisher:   CRC Number Of Pages:   288 Publication Date:   2008-09-17 ISBN-10 / ASIN:   1420044710 ISBN-13 / EAN:   9781420044713 Binding:   Hardcover Product Description: Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment.