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IC Compiler 2 CTS Student & Lab Guide 2010.03(可搜寻 PDF)

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IC Compiler 2 CTS Student & Lab Guide 2010.03(可搜寻 PDF)

At the end of this workshop the student should be able to:
  • Analyze the clock tree structure prior to running CTS
  • Check for valid clock definitions
  • Use the clock options correctly
  • Identify good vs. bad buffers/inverters for CTS
  • Specify different buffers/inverters for specific optimizations within CTS
  • Use Non-Default Routing rules (NDR) appropriately
  • Describe how to perform clock shielding, how to run low power CTS Flow and use the IC Compiler CTS flows
  • Perform clock tree synthesis in debug mode to obtain additional tool messages
  • Debug QoR problems
  • Optimize clock power before CTS and combat thermal hot-spots by controlling clock cell spacing
  • Use the interactive CTS browser to analyze and debug clock structures before and after synthesis
  • Use MultiCorner MultiMode technology with the synthesis of the clock trees



另外还有:
SystemVerilog Verification UVM 1.1 Student & Lab Guide 2011.12(可搜寻 PDF)
SystemVerilog Testbench Student & Lab Guide 2011.12(可搜寻 PDF)
Design Compiler 1 Student & Lab Guide 2012.06 (可搜寻 PDF)
IC Compiler 1 Student & Lab Guide 2010.12 (可搜寻 PDF)

IC Compiler 2 CTS Student & Lab Guide 2010.03 (可搜寻 PDF)

eetop.cn_IC Compiler 2 CTS.part1.rar

15 MB, 下载次数: 6

eetop.cn_IC Compiler 2 CTS.part2.rar

15 MB, 下载次数: 7

eetop.cn_IC Compiler 2 CTS.part3.rar

3.47 MB, 下载次数: 2

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