Writing Testbenches - Functional Verification of HDL Models(Janick Bergeron)

zhang1998

Take a survey  of the  books  about verilog  or Vhdl currently  avail-
able.  You  will  notice  that  the majority  of  the  pages  are  devoted  to
explaining  the details  of the  languages.  In addition,  several chapters
are  focused  on  the  synthesizeable  coding  style  -  or  RTL  -  replete
with examples.  Some books  are even devoted entirely  to the  subject
of RTL  coding.
When  verification  is  addressed,  only  one  or  two  chapters  are  dedi-
cated  to  the topic. And often, the primary  focus  is to introduce more
language  constructs.  Verification  is  often  presented  in  a  very  rudi-
mentary  fashion,  using  simple  techniques  that  become  tedious  in
large-scale, real-life designs.