EBook: Introduction to Logic Synthesis using Verilog HDL(Morgan & Claypool)

zhang1998

Introduction to Logic Synthesis Using verilog hdl explains how to write accurate Verilog descriptions
of digital systems that can be synthesized into digital system net lists with desirable characteristics.
The book contains numerous Verilog examples that begin with simple combinational networks
and progress to synchronous sequential logic systems. Common pitfalls in the development
of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target
audience is any one with a basic understanding of digital logic principles who wishes to learn
how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis.
A wide range of readers, from hobbyists and undergraduate students to seasoned professionals,
will find this a compelling and approachable work. This book provides concise coverage of
the material and includes many examples, enabling readers to quickly generate high-quality synthesizable
Verilog models.