【百度大脑AI计算盒FZ5C】firmware pcap 驱动代码分析

robe.zhang

【百度大脑AI计算盒FZ5C】firmware pcap 驱动代码分析

# 设备树：

1. zynqmp_pcap: pcap {
   
2.         compatible = "xlnx,zynqmp-pcap-fpga";
   
3.         clock-names = "ref_clk";
   
4. };

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# pcap 驱动 match table

1. static const struct of_device_id zynqmp_fpga_of_match[] = {
   
2.         { .compatible = "xlnx,zynqmp-pcap-fpga", },
   
3.         {},
   
4. };
   
5. 
   
6. MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);

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# platform_driver 驱动

1. static struct platform_driver zynqmp_fpga_driver = {
   
2.         .probe = zynqmp_fpga_probe,
   
3.         .remove = zynqmp_fpga_remove,
   
4.         .driver = {
   
5.                 .name = "zynqmp_fpga_manager",
   
6.                 .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
   
7.         },
   
8. };
   
9. 
   
10. module_platform_driver(zynqmp_fpga_driver);

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# probe：创建 mgr，注册 mgr

1. static int zynqmp_fpga_probe(struct platform_device *pdev)
   
2. {
   
3.         struct device *dev = &pdev->dev;
   
4.         struct zynqmp_fpga_priv *priv;
   
5.         struct fpga_manager *mgr;
   
6.         int ret;
   
7. 
   
8.         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
   
9.         if (!priv)
   
10.                 return -ENOMEM;
    
11. 
    
12.         priv->dev = dev;
    
13. 
    
14.         mgr = devm_fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
    
15.                                    &zynqmp_fpga_ops, priv);
    
16.         if (!mgr)
    
17.                 return -ENOMEM;
    
18. 
    
19.         platform_set_drvdata(pdev, mgr);
    
20. 
    
21.         ret = fpga_mgr_register(mgr);
    
22.         if (ret) {
    
23.                 dev_err(dev, "unable to register FPGA manager");
    
24.                 return ret;
    
25.         }
    
26. 
    
27.         return 0;
    
28. }
    

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# mrg 方法结构体和实现：

1. # mrg 方法结构体和实现：
   
2. struct fpga_manager_ops {
   
3.         size_t initial_header_size;
   
4.         enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
   
5.         u64 (*status)(struct fpga_manager *mgr);
   
6.         int (*write_init)(struct fpga_manager *mgr,
   
7.                           struct fpga_image_info *info,
   
8.                           const char *buf, size_t count);
   
9.         int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
   
10.         int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
    
11.         int (*write_complete)(struct fpga_manager *mgr,
    
12.                               struct fpga_image_info *info);
    
13.         int (*read)(struct fpga_manager *mgr, struct seq_file *s);
    
14.         void (*fpga_remove)(struct fpga_manager *mgr);
    
15.         const struct attribute_group **groups;
    
16. };
    
17. 
    
18. static const struct fpga_manager_ops zynqmp_fpga_ops = {
    
19.         .state = zynqmp_fpga_ops_state,
    
20.         .status = zynqmp_fpga_ops_status,
    
21.         .write_init = zynqmp_fpga_ops_write_init,
    
22.         .write = zynqmp_fpga_ops_write,
    
23.         .write_complete = zynqmp_fpga_ops_write_complete,
    
24.         .read = zynqmp_fpga_ops_read,
    
25. };

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# 每一个方法的实现：

# zynqmp_fpga_ops_state 调用 eemi_ops->fpga_get_status(&status);
# eemi_ops = zynqmp_pm_get_eemi_ops();

1. static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
   
2. {
   
3.         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
   
4.         u32 status;
   
5. 
   
6.         if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_get_status)
   
7.                 return FPGA_MGR_STATE_UNKNOWN;
   
8. 
   
9.         eemi_ops->fpga_get_status(&status);
   
10.         if (status & IXR_FPGA_DONE_MASK)
    
11.                 return FPGA_MGR_STATE_OPERATING;
    
12. 
    
13.         return FPGA_MGR_STATE_UNKNOWN;
    
14. }

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# zynqmp_pm_get_eemi_ops 返回了 eemi_ops_tbl

1. const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
   
2. {
   
3.         if (eemi_ops_tbl)
   
4.                 return eemi_ops_tbl;
   
5.         else
   
6.                 return ERR_PTR(-EPROBE_DEFER);
   
7. 
   
8. }

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# eemi_ops_tbl 就是 firmware 的方法
# zynqmp_fpga_ops_state 调用了 firmware 的方法中的 fpga_get_status 实现的
# 最终通过 zynqmp_pm_fpga_get_status 函数实现，是 firmware 的方法，最终也是调用 smc #0 实现

# 具体内容参照上一篇文章：

【百度大脑AI计算盒FZ5C】zynq-firmware 驱动代码分析

https://www.cirmall.com/bbs/thread-204685-1-1.html

# zynqmp_fpga_ops_status 调用 eemi_ops->fpga_read 实现，最终调用 zynqmp_pm_fpga_read ，又调用 smc #0 实现

1. static u64 zynqmp_fpga_ops_status(struct fpga_manager *mgr)
   
2. {
   
3.         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
   
4.         unsigned int *buf, reg_val;
   
5.         dma_addr_t dma_addr;
   
6.         u64 status = 0;
   
7.         int ret;
   
8. 
   
9.         if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_read)
   
10.                 return FPGA_MGR_STATUS_FIRMWARE_REQ_ERR;
    
11. 
    
12.         buf = dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE,
    
13.                                  &dma_addr, GFP_KERNEL);
    
14.         if (!buf)
    
15.                 return FPGA_MGR_STATUS_FIRMWARE_REQ_ERR;
    
16. 
    
17.         ret = eemi_ops->fpga_read(IXR_FPGA_CONFIG_STAT_OFFSET, dma_addr,
    
18.                                   IXR_FPGA_READ_CONFIG_TYPE, ®_val);
    
19.         if (ret) {
    
20.                 status = FPGA_MGR_STATUS_FIRMWARE_REQ_ERR;
    
21.                 goto free_dmabuf;
    
22.         }
    
23. 
    
24.         if (reg_val & IXR_FPGA_ERR_CRC_ERR)
    
25.                 status |= FPGA_MGR_STATUS_CRC_ERR;
    
26.         if (reg_val & IXR_FPGA_ERR_SECURITY_ERR)
    
27.                 status |= FPGA_MGR_STATUS_SECURITY_ERR;
    
28.         if (!(reg_val & IXR_FPGA_INIT_B_INTERNAL))
    
29.                 status |= FPGA_MGR_STATUS_DEVICE_INIT_ERR;
    
30.         if (!(reg_val & IXR_FPGA_DONE_INTERNAL_SIGNAL))
    
31.                 status |= FPGA_MGR_STATUS_SIGNAL_ERR;
    
32.         if (!(reg_val & IXR_FPGA_GST_CFG_B))
    
33.                 status |= FPGA_MGR_STATUS_HIGH_Z_STATE_ERR;
    
34.         if (!(reg_val & IXR_FPGA_END_OF_STARTUP))
    
35.                 status |= FPGA_MGR_STATUS_EOS_ERR;
    
36. 
    
37. free_dmabuf:
    
38.         dma_free_coherent(mgr->dev.parent, READ_DMA_SIZE, buf, dma_addr);
    
39. 
    
40.         return status;
    
41. }
    

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# zynqmp_fpga_ops_write_init 仅修改了一个 flags

1. static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
   
2.                                       struct fpga_image_info *info,
   
3.                                       const char *buf, size_t size)
   
4. {
   
5.         struct zynqmp_fpga_priv *priv;
   
6. 
   
7.         priv = mgr->priv;
   
8.         priv->flags = info->flags;
   
9. 
   
10.         return 0;
    
11. }

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# zynqmp_fpga_ops_write 调用 eemi_ops->fpga_load(dma_addr, size, eemi_flags);/zynqmp_pm_fpga_load 实现

1. static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
   
2.                                  const char *buf, size_t size)
   
3. {
   
4.         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
   
5.         struct zynqmp_fpga_priv *priv;
   
6.         dma_addr_t dma_addr;
   
7.         u32 eemi_flags = 0;
   
8.         size_t dma_size;
   
9.         char *kbuf;
   
10.         int ret;
    
11. 
    
12.         if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_load)
    
13.                 return -ENXIO;
    
14. 
    
15.         priv = mgr->priv;
    
16.         priv->size = size;
    
17. 
    
18.         if (priv->flags & FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM)
    
19.                 dma_size = size + ENCRYPTED_KEY_LEN;
    
20.         else
    
21.                 dma_size = size;
    
22. 
    
23.         kbuf = dma_alloc_coherent(priv->dev, dma_size, &dma_addr, GFP_KERNEL);
    
24.         if (!kbuf)
    
25.                 return -ENOMEM;
    
26. 
    
27.         memcpy(kbuf, buf, size);
    
28. 
    
29.         if (priv->flags & FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM) {
    
30.                 eemi_flags |= XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY;
    
31.                 memcpy(kbuf + size, mgr->key, ENCRYPTED_KEY_LEN);
    
32.         } else if (priv->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) {
    
33.                 eemi_flags |= XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY;
    
34.         }
    
35. 
    
36.         wmb(); /* ensure all writes are done before initiate FW call */
    
37. 
    
38.         if (priv->flags & FPGA_MGR_DDR_MEM_AUTH_BITSTREAM)
    
39.                 eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR;
    
40.         else if (priv->flags & FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM)
    
41.                 eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM;
    
42. 
    
43.         if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
    
44.                 eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
    
45. 
    
46.         if (priv->flags & FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM)
    
47.                 ret = eemi_ops->fpga_load(dma_addr, dma_addr + size,
    
48.                                           eemi_flags);
    
49.         else
    
50.                 ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags);
    
51. 
    
52.         dma_free_coherent(priv->dev, dma_size, kbuf, dma_addr);
    
53. 
    
54.         return ret;
    
55. }
    

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# zynqmp_fpga_ops_write_complete 啥也没干直接返回

1. static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
   
2.                                           struct fpga_image_info *info)
   
3. {
   
4.         return 0;
   
5. }

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# zynqmp_fpga_ops_read 调用 zynqmp_fpga_read_cfgdata 和 zynqmp_fpga_read_cfgreg 实现
# zynqmp_fpga_read_cfgdata 和 zynqmp_fpga_read_cfgreg 中调用了 eemi_ops->fpga_read / zynqmp_pm_fpga_read 实现

1. static int zynqmp_fpga_ops_read(struct fpga_manager *mgr, struct seq_file *s)
   
2. {
   
3.         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
   
4.         int ret;
   
5. 
   
6.         if (!eemi_ops || !eemi_ops->fpga_read)
   
7.                 return -ENXIO;
   
8. 
   
9.         if (readback_type)
   
10.                 ret = zynqmp_fpga_read_cfgdata(mgr, s);
    
11.         else
    
12.                 ret = zynqmp_fpga_read_cfgreg(mgr, s);
    
13. 
    
14.         return ret;
    
15. }
    
16. 
    
17. static int zynqmp_fpga_read_cfgdata(struct fpga_manager *mgr,
    
18.                                     struct seq_file *s)
    
19. {
    
20.         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
    
21.         struct zynqmp_fpga_priv *priv;
    
22.         int ret, data_offset;
    
23.         unsigned int *buf;
    
24.         dma_addr_t dma_addr;
    
25.         size_t size;
    
26. 
    
27.         priv = mgr->priv;
    
28.         size = priv->size + READ_DMA_SIZE + DUMMY_FRAMES_SIZE;
    
29. 
    
30.         buf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr,
    
31.                                  GFP_KERNEL);
    
32.         if (!buf)
    
33.                 return -ENOMEM;
    
34. 
    
35.         seq_puts(s, "zynqMP FPGA Configuration data contents are\n");
    
36.         ret = eemi_ops->fpga_read((priv->size + DUMMY_FRAMES_SIZE) / 4,
    
37.                                   dma_addr, readback_type, &data_offset);
    
38.         if (ret)
    
39.                 goto free_dmabuf;
    
40. 
    
41.         seq_write(s, &buf[data_offset], priv->size);
    
42. 
    
43. free_dmabuf:
    
44.         dma_free_coherent(mgr->dev.parent, size, buf, dma_addr);
    
45. 
    
46.         return ret;
    
47. }
    
48. 
    
49. static int zynqmp_fpga_read_cfgreg(struct fpga_manager *mgr,
    
50.                                    struct seq_file *s)
    
51. {
    
52.         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
    
53.         int ret, val;
    
54.         unsigned int *buf;
    
55.         dma_addr_t dma_addr;
    
56.         struct zynqmp_configreg *p = cfgreg;
    
57. 
    
58.         buf = dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE,
    
59.                                  &dma_addr, GFP_KERNEL);
    
60.         if (!buf)
    
61.                 return -ENOMEM;
    
62. 
    
63.         seq_puts(s, "zynqMP FPGA Configuration register contents are\n");
    
64. 
    
65.         while (p->reg) {
    
66.                 ret = eemi_ops->fpga_read(p->offset, dma_addr, readback_type,
    
67.                                           &val);
    
68.                 if (ret)
    
69.                         goto free_dmabuf;
    
70.                 seq_printf(s, "%s --> \t %x \t\r\n", p->reg, val);
    
71.                 p++;
    
72.         }
    
73. 
    
74. free_dmabuf:
    
75.         dma_free_coherent(mgr->dev.parent, READ_DMA_SIZE, buf,
    
76.                           dma_addr);
    
77. 
    
78.         return ret;
    
79. }

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能看懂 C 语言不重要，重要的是代码要表达的意思，看总结

# 总结：

1，pcap 主要实现 fpga 管理功能

2，这些功能的实现最终调用 firmware 实现