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Senior Physical Design Engineer
Location: Shanghai/Nanjing
Department: Switching R&D
Essential skills:
MS in EE required.
·Proven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
·Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
·Good programming skill.
·Capable of writing Tcl or Perl.
·Familiar with synthesis, static timing analysis.
·Self-motivated team worker, good verbal and written communication skills in English.
·Technical and team leadership proffered. Previous management experience highly desired.
·Experience with synthesis, DFT, and verification is preferred.
Key Responsibilities
Depending on experience, key responsibilities will involve some of the following:
·IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
·As a key member of physical design team, your will work on one of most advanced and the most complex chip Marvell designed.
·Leading a team of physical design engineers and resolving the technical related issues.
·Crosstalk analysis, power analysis, and static timing analysis.
·Write scripts in Tcl to improve productivity.
If you have any interest in the position, please send your bilingual resume as attachments to emilyye@marvell.com
Subject of your email should be “Your Name_University_Applied Position Title”
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