全职 Synopsys Subsystem Design Engineer 北京/深圳/上海

Candyqin

 Job Title: Synopsys Subsystem Design Engineer
Job Location: Shanghai/Beijing/Shenzhen
接受简历地址： zhuqin.tang@synopsys.com

JD:

Are you a creative, highly motivated individual with a passion for “doing it right”?

Do you thrive in an environment where delivering customer satisfaction “goes without saying”?

As a Subsystem Implementation CAE in the Solutions Group at Synopsys, you will be responsible for the successful implementation of IP Subsystems involving both digital controller and mixed signal physical layer IPs selected from our broad portfolio of interface IP. You will also work closely with Marketing and R&D teams to collaborate on IP customizations, integration, verification and implementation of IP Subsystems. You will analyze and resolve complex Subsystem usage/implementation issues and provide timely, accurate technical guidance to customers. You will also be responsible for contributing to the authoring of the associated Subsystem documentation such as user guides, application notes and white papers that promote the Subsystems' ease of use, or address specific challenges in its implementation. You will have regular contact with external customers and internal contacts across cross-functional teams. Occasional travel will be required.

Responsibilities Include

· Implementation of complex IP subsystems including the design additional blocks as necessary to meet with the design specification.

· Hands-on RTL design and coding of additional functional logic blocks.

· Debug designs in simulation, emulation and silicon.

· Participate in design specification, verification plan, code and coverage reviews.

· Proactively engaging with customers during integration and silicon debug.



Education and Experience

· Bachelors and/or Master’s Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science.

· Minimum of 5 years relevant experience in ASIC/SoC front-end design including RTL coding in Verilog, logic and clock tree synthesis, static timing analysis, equivalence checking.

· Full understanding of digital design methodologies and tools including formal verification.

· Domain knowledge of at least one of the following protocols:

o    DDR - DDR3, DDR4, LPDDR2, LPDDRR3

o    PCI Express – Gen2, Gen3

o    USB – 2.0, 3.0

· Ideally have experienced at least one ASIC/SoC tape-out from concept to full production.

· Silicon debug and troubleshooting skills are highly desirable.

· Technically creative, results oriented with the ability to manage multiple tasks efficiently including customer support issues and priorities.

· Strong communication skills and ability to interact with customers as well as peers.

· Adaptability to fast moving, changing environment with constant challenge.

· High degree of self-motivation and personal responsibility.

· Have the ability to work well within a team environment.