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ic猎头公司上海吉优人才服务有限公司代理职位

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发表于 2007-12-11 20:00:34 | 显示全部楼层 |阅读模式
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Senior FAE
公司简介: 美资IC公司,欲NASDQ上市公司。
工作地点: SHANGHAI
职位要求: a pre ipo company is looking for applications engineers for supporting our tuner related products, including both hardware and software development.  The development efforts include but not limited to designing reference boards, generating reference kits, debugging customer board design, writing applications notes, develop application software for evaluation, and writing software in C++ and Labview for test automation.  Experience and knowledge working with RF circuits and RF systems is a strong plus.  Excellent written and verbal communications skills are also required.  This job may require traveling to customer sites for up to 30-40% of the time.   
                       

                       
 
 
                                                FPGA Design Engineer                       
                       
公司简介: 美资IC公司,欲NASDQ上市公司。
工作地点: SHANGHAI
职位要求:                                                  Looking for an FPGA design engineer. Should have good understanding of the whole FPGA design flow,i.e, including RTL coding, simulation, synthesis, timing closure, and FPGA verification. Should be proficient in all aspects of FPGA design, have an in-depth familiarity with Xilinx FPGAs (particularly the Virtex family) and also an in-depth knowledge of Synplicity, and Xilinx ISE. Should have good background in communication theory and embeded systems. Should be proficient in the lab in terms of FPGA emulation and IC testing. A self starter, motivated,hardworking and good team player. BSEE required, MSEE prefered.  3 years industrial experience.
                       
                       
                       
                       
                       
                       
                       

                       
                       
                       
 
Backend Design Engineer
公司简介: 美资IC公司,欲NASDQ上市公司。
工作地点: SHANGHAI
职位要求:                                                Looking for an ASIC backend design engineer. Should have good understanding of backend ASIC design flow, i.e., floor planning, clock tree synthesis, place and route, SI analysis, timing closure, LVS, DRC. Should be familiar with either Cadence flow or Synopsys flow. A self starter, motivated, hardworking good team player. Should have taped out at least 2 chips independently. BSEE required, MSEE prefered. 5 years industrial experience.                        
                       



请发送简历到yuxin.huang@ji-you.cn
月薪20k以上,有股票期权,美国培训,有sign bonus。
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