月薪20k招聘FPGA设计工程师（上海）

jiyou

Looking for an FPGA design engineer.


Should have good understanding of the whole FPGA design flow,i.e, including RTL


coding, simulation, synthesis, timing closure, and FPGA verification.


Should be proficient in all aspects of FPGA design, have an in-depth familiarity


with Xilinx FPGAs (particularly the Virtex family) and also an in-depth knowledge


of Synplicity, and Xilinx ISE.


Should have good background in communication theory


and embeded systems. Should be proficient in the lab in terms of FPGA emulation


and IC testing. A self starter, motivated,hardworking and good team player.


BSEE required, MSEE prefered.
3 years industrial experience.

请投递简历到 yuxin.huang@ji-you.cn

上海职位，有股票期权，入职后美国培训。
FPGA flow比较精通外，板级设计能力调试能力要强。
fpga很熟或者做asic的，板级不强不考虑。