Whenever a vertical and a horizontal channel intersect, there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.
Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed IO logic and embedded memories.
FPGAs are also widely used for systems validation including pre-silicon validation, post-silicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time to market.
[size=67%][edit]FPGA design and programming
To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form might be easier to work with when handling large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. On the other hand, schematic entry can allow for easier visualisation of a design.
Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA.
Going from schematic/HDL source files to actual configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. This file is then transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM.
The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages.
To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free, and typically released under proprietary licenses). Other predefined circuits are available from developer communities such as OpenCores (typically free, and released under the GPL, BSD or similar license), and other sources.
In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.
[size=67%][edit]Basic process technology types
- SRAM - based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS.
- Antifuse - One-time programmable. CMOS.
- EPROM - Erasable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
- EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS.
- Flash - Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
- Fuse - One-time programmable. Bipolar.
[size=67%][edit]Manufacturers and their specialties
As of late 2005, the FPGA market has mostly settled into a state where there are two major "general-purpose" FPGA manufacturers and a number of other players who differentiate themselves by offering unique capabilities.
- Xilinx and Altera are the current FPGA market leaders. Xilinx also provides free Windows and Linux design software [2], while Altera provides free Windows tools; the Solaris and Linux tools are only available via a rental scheme. [3].
- Lattice Semiconductor provides SRAM with embedded non-volatile flash configuration memory on board.
- Actel has antifuse and reprogrammable flash-based FPGAs, and also offers mixed signal flash-based FPGAs.
- Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx were. They focus on providing Atmel AVR Microcontrollers with FPGA fabric on the same die.
- QuickLogic has antifuse (programmable-only-once) products and heavily focused on handheld applications.
- Achronix Start Up -- focuses on very high speed > 1GHZ clock rate FPGA technology
- Silicon Blue Start Up -- focuses on low power mobile device FPGA technology
[size=67%][edit]See also
[size=67%][edit]Notes
Resources
[size=76%][edit]Software Tools
- Agility Design Solutions - DK Design Suite for Handel C to FPGA synthesis
- Sourceforge - Free tools and cores for FPGAs
- 3L Diamond - Diamond interactive design environment (IDE) for multiprocessor systems (Diamond DSP: RTOS for a network of DSP devices; Diamond FPGA: combining the power of DSP and FPGA devices)
- Altium Designer - Design suite for Altera, Xilinx, Actel, Lattice FPGA/CPLD families
- Quartus - Design suite for Altera devices
- ISE - Design suite for Xilinx devices
- ispLEVER - Design suite for Lattice devices
- Libero IDE Actel - Design suite for Actel devices
- LogicSim - FPGA simulation tool
- ModelSim - Mixed-languages simulator
- Synplify - FPGA synthesis tool
- LabVIEW FPGA - Graphical Programming FPGAs on COTS Hardware
- C-to-Verilog - On-line tool for Programming FPGAs in C
[size=76%][edit]Media
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发表于 2009-1-14 04:19:29
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