Intel的45nm之路

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Intel总是领导者半导体技术的发展，随着半导体工艺迈向65nm, 45nm, 32nm，摩尔定律如何得到保证以及如何才是正确的解释？在量子效应控制的微观世界，采用什么样的工艺才能保证速度、性能的提高、成品率不降低，漏电流得到有效的控制？
相信人类的智慧能够克服一切困难，最终会找到满意的解决方案， 无疑Intel在半导体方面是主导着，一如既往地。

Intel’s path to 45nm: why the big lead, and how? Restrictive design rules, perhaps?

Oct 10 2007  4:34PM

There has been intense speculation in process engineering circlesabout just what Intel is doing in process development. The pitch onthis guessing-game will increase as we get closer to this year’s IEDMconference, where the company is scheduled to give several papers ontheir 45nm process. But in the meantime, we should make someobservations.
 
To start with, a few things are known. Intel appears to be furtheralong toward production with a real 45nm process than anyone else. Theyalso appear to be getting far better results, in terms ofpower-performance and yield, on 65nm than almost anyone else—certainlybetter than AMD, which rumor says is in serious trouble over 65nmyields and is not finding its way out.
 
We also know, from company statements, that Intel is not usingimmersion lithography even in critical layers at 65nm, although theyare apparently, according to at least one report,using it at 45nm. Assuming that Intel process developers are using thesame physics as the rest of us, what the heck is going on?
 
The most plausible answer I’ve heard is that Intel attacked the 65nmand 45nm yield problem from a number of fronts simultaneously. Insteadof trying to find a level of OPC that would produce perfect arbitraryshapes, they optimized the complex surface of lithographic techniques,OPC techniques, and circuit tolerances to give them working silicon forthe minimum equipment cost, loss of throughput and elaborateness ofdecoration. This seems to have resulted in a choice of strongphase-shifting, some carefully-chosen OPC techniques, and for mostlayers, dry lithography.
 
This is entirely in line with an argument put forward by Luminescent Technology’snew CEO, Moris Kori, that the ability to explore the entire solutionspace for local optima is vital to finding the right process decisions.Kori is of course arguing in favor of one of his products, which allowsdesigners to feed information on mask technologies, optical columns,exposure techniques and illumination, OPC techniques into anexploration tool and compare simulated results for actual patterns. Buthis point stands independent of his financial interest.
 
But I don’t think that is the entire story. There is pretty goodcircumstantial evidence that Intel is also using one more degree offreedom, one that has been anathema to many designers: restrictivedesign rules. For example, in a January, 2007 paper here,Intel authors Farhang and Deeter said “Defining Robust (sometimesreferred to as Restrictive) design rules (RDR) that mitigate thevariability challenges is the foundation of our DFM strategy.”
 
Could this be a silver bullet to delaying immersion lithography,improving yield and reducing variability? Well, yes it could, if you infact have your process engineers, your product engineers, your librarydevelopment team and your custom circuit designers all in oneorganization, and if you are willing to impose sufficient discipline onthem all. Given these criteria, the process Farhang and Deeter describeof co-optimizing the process, the development cycle and the productdesign can work.
 
If you use rules that restrict the number of patterns that can occuron a mask, you free lithography experts and process engineers fromhaving to come up with a process that can do everything—they canconcentrate on doing only the patterns that are allowed. Needless tosay that is a huge reduction of the domain of the problem, and freesyou from having to throw every technology you can get at the solution.
 
In the past, we have mainly heard discussions about whether nastyrestrictive design rules—intrusions on freedom of expression—wouldeventually become necessary at some distant future process node. Theconsensus has been that they might, but they’d better not becausedesigners would fight them. Now we are faced with the possibility thatwhile we were debating personal freedom, Intel worked out that a severerestriction of the design space would have substantial advantages ontoday’s processes, and put that observation into practice. If that isthe case, there is at least a marvelous irony in it.
 



读者的评论：

at 10/11/2007 2:48:48 PM, Kari A. said:
Ron -- I work for Intel and found your post to be a very interestingread. I agree with many of the points you make, particularly about thevalue of DFM and co-optimization to obtain the best results.One point I do want to clarify, though, is that Intel is NOT usingimmerision lithography on any layers at the 45nm node. We are using193nm dry lithography at 45nm because we were able to scale it foranother generation. We have said that critical masking layers in the32nm SRAM and logic chip that we just showed a couple of weeks ago atthe Intel Developer Forum use 193 nm immersion lithography, while lesscritical layers use 193nm dry or 248 nm dry lithography.

at 10/11/2007 3:31:41 PM, ron said:
Kari:Thank you for the clarification. In the literature there are directlycontradictory statements about Intel's plans at 45nm, so it's great tohear it from the source!

at 10/12/2007 12:36:29 PM, JumpingJack said:
Intel isremaining dry at 45 nm: Quoted from Intel's 45 nm presskit on the 45 nmannouncement (your bot will not allow links):"It will also use innovative design rules and advanced mask techniquesto extend the use of 193nm dry lithography to manufacture its 45nmprocessors because of the cost advantages and high manufacturability itaffords. "But in all, there must be definitive advantages to having the wholeshow in house, and the design processes playing out both at the TCADthrough to the circuit and process level

at 10/12/2007 12:38:53 PM, JumpingJack said:
Follow up --In fact, I recall reading a Dec 2006 IEDM paper from Intel regardingusing dry 193 nm litho for the 45 nm process, I can forward you thereference if you so like (would take me a bit to look it up).Jack

at 10/12/2007 6:47:12 PM, debugger said:
There is doublepatterning used in Intel''s 45 nm transistor patterning. Twophotoresist coatings and exposures. Also processing for two differentgate metals.