CDCM6100XEVM评估模块

GY@艳

CDCM6100XEVM是CDCM61004或CDCM61002或CDCM61001的评估模块。该CDCM6100x评估模块（EVM）旨在演示了CDCM61004的电气性能和具有代表性的CDCM61001和CDCM61002的表现。DescriptionCDCM6100xEVM is the evaluation module for CDCM61004 or CDCM61002 or CDCM61001. CDCM61004/2/1 family is a highly versatile, ultra low-jitter frequency synthesizer family that can generate four/two/one low-jitter clock output pairs, selectable among LVPECL, LVDS, or 2 LVCMOS, from a low-frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM6100x features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The pin-pin compatible CDCM6100x is available in a small, 32-pin, 5mmx5mm QFN package. The CDCM6100x is a programmable clock generator with control pins only. No EEPROM or programming interface is necessary to program these devices. The CDCM6100x evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCM61004 and is representative of the performance of the CDCM61001 and CDCM61002. The only difference among these 3 devices is the number of outputs. This fully-assembled and factory-tested evaluation board allows complete validation of all device functions. Features

       

• Input frequency range: 21.875 MHz to 28.47 MHz; Crystal reference input example: 24.8832 MHz, 25 MHz, or 26.5625 MHz       
  
• Fully intergrated VCO operating in frequency range of 1.75 GHz to 2.05 GHz Supported output frequency from 43.75 - 683.264MHz. Examples: 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz, 625 MHz       
  
• Pin-selectable between LVPECL, LVDS, or 2-LVCMOS       
  
• Input bypass output available that allows direct crystal tuning       
  
• Internal PLL Loop Bandwidth: 400 kHz       
  
• Phase Noise typically at -146 dBc/Hz at 5-MHz Offset for 625-MHz LVPECL Output Random Jitter typically at 0.509 ps, RMS (10 kHz to 20 MHz) for 625-MHz LVPECL Output Output Duty Cycle Corrected to 50% (+/-5%)       
  
• Low output skew of 30 ps on LVPECL outputs       
  
• Single 3.3-V power supply; Industrial temperature range: -40C to +85C       
  
• 5mmx5mm, 32-pin, QFN (RHB) package 10. ESD protection exceeds 2 kV (HBM)