CDCLVD1212评估模块

GY@艳

CDCLVD1212评估模块（EVM）旨在展示CDCLVD1212或CDCLVD2106的电气性能。该CDCLVD1212/CDCLVD2106是高性能，低附加抖动时钟缓冲器。该器件还具有片上偏置发生器，可以提供LVDS共模电压的设备投入。DescriptionThe CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can provide the LVDS common-mode voltage to the device inputs. The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1212 or CDCLVD2106. However, this EVM can also be used for customers interested in the CDCLVD1216 or CDCLVD2108 as well. This fully assembled and factory-tested evaluation board allows complete validation of device functionalities. For optimum performance, the board is equipped with SMA connectors and well-controlled 50-ohm impedance microstrip transmission lines. Features

       

• Easy-to-use evaluation board to fan out low-phase noise clocks       
  
• Easy device setup       
  
• Fast configuration       
  
• Control pins configurable through jumpers       
  
• Board powered at 2.5 V       
  
• Single-ended or differential input clocks       
  
• Device supports twelve LVDS outputs, EVM supports four LVDS outputs