CDCLVP1212评估模块

GY@艳

CDCLVP1212评估模块（EVM）被设计来演示CDCLVP1212的电性能。DescriptionThe CDCLVP1212 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP1212. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP1212 device functionalities. For optimum performance, the board is equipped with 50-ohm SMA connectors and well-controlled, 50-ohm impedance microstrip transmission lines. Features

       

• Easy-to-use evaluation board to fan out low phase noise clocks       
  
• Easy device setup       
  
• Fast configuration       
  
• Control pins configurable through jumpers       
  
• Board powered at +2.5-V/+3.3-V       
  
• Single-ended or differential input clocks       
  
• CDCLVP1212 supports 12 LVPECL outputs; CDCLVP1212EVM supports four LVPECL outputs