CDCLVP1102EVM评估模块

GY@艳

CDCLVP1102EVM为用户提供了接收差分或单端时钟作为时钟输入的选项。默认选项是在两个设备输入差分信号。该输入可以通过形状记忆合金（J103，J104）被应用。这些输入是交流耦合到设备的投入。The CDCLVP1102EVM offers users the option of receiving either a differential or single-ended clock as the clock input. The default option is for the differential signal at both device inputs. The inputs can be applied through the SMAs (J103, J104). These inputs are ac-coupled to the device inputs. The common-mode voltage for these inputs after the ac-coupling capacitors are provided by 50 Ω (R154,R155) to the device on-chip bias generator (VAC_REF) pin.