一个用EDA做的时钟课程设计

小鹿快跑

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shizhong is
port( clk      :in std_logic;                       --系统时钟4M         
      outm     ut std_logic_vector(6 downto 0);
      outm1    ut std_logic_vector(6 downto 0);
      outf    ut std_logic_vector(6 downto 0);
      outf1    ut std_logic_vector(6 downto 0);
      outs    ut std_logic_vector(6 downto 0);
      outs1    ut std_logic_vector(6 downto 0)
      );  
end shizhong ;
architecture miao of shizhong is
signal seg0:std_logic_vector(3 downto 0);
signal seg1:std_logic_vector(2 downto 0);
signal seg2:std_logic_vector(3 downto 0);
signal seg3:std_logic_vector(2 downto 0);
signal seg4:std_logic_vector(3 downto 0);
signal seg5:std_logic_vector(1 downto 0);
begin      
process(clk)
begin
if clk'event and clk='1' then
    seg0<=seg0+'1';
    if (seg0="1001") then
    seg0<="0000";
    seg1<=seg1+'1';
   if (seg1="110") then
     seg1<="000";
     seg2<=seg2+'1';
      if (seg2="1001") then
      seg2<="0000";
      seg3<=seg3+'1';
       if (seg3="110") then
       seg3<="000";
       seg4<=seg4+'1';
        if (seg4="1001") then
        seg4<="0000";
        seg5<=seg5+'1';
        end if;
       end if;
      end if;
   end if;
    end if;
end if;
end process;
process(clk)
begin
  if clk'event and clk='1'  then  
   case seg0 is
     when "0000" =>outm<="1001111"; --0
     when "0001" =>outm<="0010010"; --1
     when "0010" =>outm<="0000110"; --2
     when "0011" =>outm<="1001100"; --3
     when "0100" =>outm<="0100100"; --4
     when "0101" =>outm<="0100000"; --5
     when "0110" =>outm<="0001111"; --6
     when "0111" =>outm<="0000000"; --7
     when "1000" =>outm<="0000100"; --8
     when "1001" =>outm<="0001000"; --9
     when others=>null;
   end case;
  end if;
end process;
process(clk)
begin
  if clk'event and clk='1'  then  
   case seg1 is
     when "000" =>outm1<="1001111"; --0
     when "001" =>outm1<="0010010"; --1
     when "010" =>outm1<="0000110"; --2
     when "011" =>outm1<="1001100"; --3
     when "100" =>outm1<="0100100"; --4
     when "101" =>outm1<="0100000"; --5
     when "110" =>outm1<="0001111"; --6
   --  when "0111" =>outm<="0000000"; --7
    -- when "1000" =>outm<="0000100"; --8
    -- when "1001" =>outm<="0001000"; --9
     when others=>null;
   end case;
  end if;
end process;
process(clk)
begin
  if clk'event and clk='1'  then  
   case seg2 is
     when "0000" =>outf<="1001111"; --0
     when "0001" =>outf<="0010010"; --1
     when "0010" =>outf<="0000110"; --2
     when "0011" =>outf<="1001100"; --3
     when "0100" =>outf<="0100100"; --4
     when "0101" =>outf<="0100000"; --5
     when "0110" =>outf<="0001111"; --6
     when "0111" =>outf<="0000000"; --7
     when "1000" =>outf<="0000100"; --8
     when "1001" =>outf<="0001000"; --9
     when others=>null;
   end case;
  end if;
end process;
process(clk)
begin
  if clk'event and clk='1'  then  
   case seg3 is
     when "000" =>outf1<="1001111"; --0
     when "001" =>outf1<="0010010"; --1
     when "010" =>outf1<="0000110"; --2
     when "011" =>outf1<="1001100"; --3
     when "100" =>outf1<="0100100"; --4
     when "101" =>outf1<="0100000"; --5
     when "110" =>outf1<="0001111"; --6
   --  when "111" =>outf1<="0000000"; --7
   --  when "000" =>outf1<="0000100"; --8
   --  when "001" =>outf1<="0001000"; --9
     when others=>null;
   end case;
  end if;
end process;
process(clk)
begin
  if clk'event and clk='1'  then  
   case seg4 is
     when "0000" =>outs<="1001111"; --0
     when "0001" =>outs<="0010010"; --1
     when "0010" =>outs<="0000110"; --2
     when "0011" =>outs<="1001100"; --3
     when "0100" =>outs<="0100100"; --4
     when "0101" =>outs<="0100000"; --5
     when "0110" =>outs<="0001111"; --6
     when "0111" =>outs<="0000000"; --7
     when "1000" =>outs<="0000100"; --8
     when "1001" =>outs<="0001000"; --9
     when others=>null;
   end case;
  end if;
end process;
process(clk)
begin
  if clk'event and clk='1'  then  
   case seg5 is
     when "00" =>outs1<="1001111"; --0
     when "01" =>outs1<="0010010"; --1
     --when "0010" =>outs<="0000110"; --2
     --when "0011" =>outs<="1001100"; --3
     --when "0100" =>outs<="0100100"; --4
     --when "0101" =>outs<="0100000"; --5
     --when "0110" =>outs<="0001111"; --6
     --when "0111" =>outs<="0000000"; --7
     --when "1000" =>outs<="0000100"; --8
     --when "1001" =>outs<="0001000"; --9
     when others=>null;
   end case;
  end if;
end process;
end miao;