Verilog基础--ps/2键盘

libing64 · 发表于 2013-4-23 23:49:48

看了看黑金的ps2程序，没看懂，决定使用特权同学的代码
ps2模块

`timescale 1ns / 1ps
module ps2
(
CLK,
RSTn,
iCe,
pclk,
pdata,
scan_code,
rdy
);
input CLK; //50M时锟斤拷锟脚猴拷
input RSTn; //锟斤拷位锟脚猴拷
input pclk; //PS2锟接匡拷时锟斤拷锟脚猴拷
input pdata; //PS2锟接匡拷锟斤拷锟斤拷锟脚猴拷
input iCe;
wire wGatedClk;
reg rCe;
output reg[15:0] scan_code; // 1byte锟斤拷值锟斤拷只锟斤拷锟津单的帮拷锟斤拷扫锟斤拷
wire oPsState; //锟斤拷锟教碉拷前状态锟斤拷ps2_state=1锟斤拷示锟叫硷拷锟斤拷锟斤拷锟斤拷
//------------------------------------------
reg rPsClk0,rPsClk1,rPsClk2; //ps2k_clk状态锟侥达拷锟斤拷
//wire pos_ps2k_clk; // ps2k_clk锟斤拷锟斤拷锟截憋拷志位
wire neg_ps2k_clk; // ps2k_clk锟铰斤拷锟截憋拷志位
always @ (posedge CLK)
begin
rCe <= iCe;
end
assign wGatedClk = rCe & CLK;
always @ (posedge wGatedClk or negedge RSTn) begin
if(!RSTn) begin
rPsClk0 <= 1'b0;
rPsClk1 <= 1'b0;
rPsClk2 <= 1'b0;
end
else begin //锟斤拷锟斤拷状态锟斤拷锟斤拷锟斤拷锟剿诧拷
rPsClk0 <= pclk;
rPsClk1 <= rPsClk0;
rPsClk2 <= rPsClk1;
end
end
assign neg_ps2k_clk = ~rPsClk1 & rPsClk2; //锟铰斤拷锟斤拷
//------------------------------------------
reg[7:0] ps2_byte_r; //PC锟斤拷锟斤拷锟斤拷锟絇S2锟斤拷一锟斤拷锟街斤拷锟斤拷锟捷存储锟斤拷
reg[7:0] temp_data; //锟斤拷前锟斤拷锟斤拷锟斤拷锟捷寄达拷锟斤拷
reg[3:0] num; //锟斤拷锟斤拷锟侥达拷锟斤拷
output rdy;
reg rdy;
always @ (posedge wGatedClk or negedge RSTn) begin
if(!RSTn) begin
num <= 4'd0;
temp_data <= 8'd0;
end
else if(neg_ps2k_clk) begin //锟斤拷锟解到ps2k_clk锟斤拷锟铰斤拷锟斤拷
case (num)
4'd0: num <= num+1'b1;
4'd1: begin
num <= num+1'b1;
temp_data[0] <= pdata; //bit0
end
4'd2: begin
num <= num+1'b1;
temp_data[1] <= pdata; //bit1
end
4'd3: begin
num <= num+1'b1;
temp_data[2] <= pdata; //bit2
end
4'd4: begin
num <= num+1'b1;
temp_data[3] <= pdata; //bit3
end
4'd5: begin
num <= num+1'b1;
temp_data[4] <= pdata; //bit4
end
4'd6: begin
num <= num+1'b1;
temp_data[5] <= pdata; //bit5
end
4'd7: begin
num <= num+1'b1;
temp_data[6] <= pdata; //bit6
end
4'd8: begin
num <= num+1'b1;
temp_data[7] <= pdata; //bit7
end
4'd9: begin
num <= num+1'b1; //锟斤拷偶校锟斤拷位锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷
end
4'd10: begin
num <= 4'd0; // num锟斤拷锟斤拷
end
default: ;
endcase
end
end
always @ (posedge wGatedClk or negedge RSTn)
begin
if(!RSTn)
begin
rdy <= 1'b0;
end
else if(num == 4'd10)
rdy <= 1'b1;
else rdy <= 1'b0;
end
reg key_f0; //锟缴硷拷锟斤拷志位锟斤拷锟斤拷1锟斤拷示锟斤拷锟秸碉拷锟斤拷锟斤拷8'hf0锟斤拷锟劫斤拷锟秸碉拷锟斤拷一锟斤拷锟斤拷锟捷猴拷锟斤拷锟斤拷
reg ps2_state_r; //锟斤拷锟教碉拷前状态锟斤拷ps2_state_r=1锟斤拷示锟叫硷拷锟斤拷锟斤拷锟斤拷
reg[20:0] k;
always @ (posedge wGatedClk or negedge RSTn) begin //锟斤拷锟斤拷锟斤拷锟捷碉拷锟斤拷应锟斤拷锟斤拷锟斤拷锟斤拷只锟斤拷1byte锟侥硷拷值锟斤拷锟叫达拷锟斤拷
if(!RSTn) begin
key_f0 <= 1'b0;
ps2_state_r <= 1'b0;
end
else if(num==4'd9) begin //锟秸达拷锟斤拷锟斤拷一锟斤拷锟街斤拷锟斤拷锟斤拷
if(temp_data == 8'hf0) key_f0 <= 1'b1;
else begin
if(!key_f0) begin //说锟斤拷锟叫硷拷锟斤拷锟斤拷
if(k>=4000)
begin
ps2_state_r <= 1'b1;
ps2_byte_r <= temp_data;
end //锟斤拷锟芥当前锟斤拷值
else
k<=k+1'b1;
end
else if(key_f0) begin
ps2_state_r <= 1'b0;
key_f0 <= 1'b0;
k<=0;
end
end
end
end
reg[15:0] ps2_asci; //锟斤拷锟斤拷锟斤拷锟捷碉拷锟斤拷应ASCII锟斤拷
always @ (ps2_byte_r)
begin
/*case (ps2_byte_r) //锟斤拷值转锟斤拷为ASCII锟诫，锟斤拷锟斤拷锟斤拷锟侥比较简单ｏ拷只锟斤拷锟斤拷锟斤拷母
8'h5a: ps2_asci <= 16'hfffe;
8'h71: ps2_asci <= 16'hfffd;
8'h70: ps2_asci <= 16'hfffb;
8'h66: ps2_asci <= 16'hfff7;
8'h79: ps2_asci <= 16'hffef;
8'h7a: ps2_asci <= 16'hffdf;
8'h72: ps2_asci <= 16'hffbf;
8'h69: ps2_asci <= 16'hff7f;
8'h74: ps2_asci <= 16'hfeff;
8'h73: ps2_asci <= 16'hfdff;
8'h6b: ps2_asci <= 16'hfbff;
8'h7d: ps2_asci <= 16'hf7ff;
8'h75: ps2_asci <= 16'hefff;
8'h6c: ps2_asci <= 16'hdfff;
8'h7b: ps2_asci <= 16'hbfff;
8'h7c: ps2_asci <= 16'h7fff;
default:ps2_asci<=16'hffff ;
endcase*/
ps2_asci <= {8'hff,ps2_byte_r[7:0]};
end
assign oPsState = ps2_state_r;
//assign scan_code = ps2_asci;
always@(posedge wGatedClk)
begin
if(oPsState==1)
scan_code <= ps2_asci;
else
scan_code <=16'hffff;
end
endmodule

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写一个命令测试模块

module cmd_control_module
(
CLK, RSTn,
PS2_Done_Sig, PS2_Data,
Data_Out
);
input CLK;
input RSTn;
input PS2_Done_Sig;
input [7:0]PS2_Data;
output [3:0]Data_Out;
/*****************************/
reg [3:0]rData;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rData <= 4'b0001;
end
else if( PS2_Done_Sig )
case( PS2_Data )
8'h1d:
rData <= { rData[2:0], rData[3] };
8'h22:
rData <= { rData[0], rData[3:1] };
8'h14:
rData <= { rData[0], rData[1], rData[2], rData[3] };
endcase
/***********************************/
assign Data_Out = rData;
/***********************************/
endmodule

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再写一个顶层模块：

module top(
pclk,
pdata,
parity_error,
CLK,
RSTn,
LED
);
input pclk; // PS_2 clock input
input pdata; // PS_2 pdata input
wire[7:0] scan_code; // Scan_code output
output parity_error; // Parity output
wire rdy; // pdata ready output
// ps P(
// .pclk(pclk),
// .pdata(pdata),
// .scan_code(scan_code),
// .parity_error(parity_error),
// .rdy(rdy)
// );
ps2 P(
.CLK(CLK),
.RSTn(RSTn),
.iCe(1'b1),
.pclk(pclk),
.pdata(pdata),
.scan_code(scan_code),
.rdy(rdy)
);
output [3:0] LED;
input CLK, RSTn;
cmd_control_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.PS2_Done_Sig( rdy ), // input - from U1
.PS2_Data( scan_code ), // input - from U1
.Data_Out( LED ) // output - to top
);
endmodule

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按下W时，LED向右奔跑，X向走奔跑，按下ctrl时左右交换
tcl文件

#------------------GLOBAL--------------------#
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
#复位引脚
set_location_assignment PIN_M1 -to RSTn
#时钟引脚
set_location_assignment PIN_R9 -to CLK
#数码管对应的引脚
#LED对应的引脚
set_location_assignment PIN_J1 -to LED[0]
set_location_assignment PIN_J2 -to LED[1]
set_location_assignment PIN_K1 -to LED[2]
set_location_assignment PIN_K2 -to LED[3]
#PS2对应的引脚
set_location_assignment PIN_E7 -to pdata
set_location_assignment PIN_D8 -to pclk

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Verilog写了两天了，明天把VGA、LCD、串口写出来，可以写几个综合的模块了

libing64 · 发表于 2013-4-23 23:50:36

刚写Verilog时很不习惯，谢谢就好了了，不过真心感觉黑金动力社区的例程很磨叽~

hymansmith · 发表于 2013-4-25 23:12:19

lo楼主加油

晴晴ら公主 · 发表于 2013-5-5 23:06:57

呵呵，非常感谢，很好很强大

Verilog基础--ps/2键盘

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