TA的每日心情 | 开心 2014-5-14 13:12 |
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签到天数: 180 天 连续签到: 1 天 [LV.7]常住居民III
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- module runLED
- (
- CLK, RSTn, LED
- );
- input CLK, RSTn;
- output [3:0] LED;
-
- parameter T1s = 26'd50_000_000;
- reg [31:0] count;
-
-
- always @(posedge CLK or negedge RSTn)
- if(!RSTn)
- count <= 0;
- else if (count == T1s)
- count <= 26'b0;
- else count <= count + 26'b1;
-
- reg[3:0] rLED;
- always @(posedge CLK or negedge RSTn)
- if(!RSTn)
- rLED <= 4'b0001;
- else if(count == T1s)
- begin
- if(rLED == 4'b0000)
- rLED <= 4'b0001;
- else
- rLED <= {rLED[2:0], 1'b0};
- end
- assign LED = rLED;
- endmodule
-
复制代码 最近买了黑金动力社区的开发板,学一学Verilog的基本逻辑,以前一直在用Sysgen做图像处理算法方面,有点走火入魔,回头发现其实用Verilog写图像处理也是可以的,因此决定认真学习Verilog,首先是学习黑金动力的例程,说实话,C语言看久了,就感觉它的代码很磨叽,因此决定自己写。虽然简单,但是还算好理解。
tcl代码:- #------------------GLOBAL--------------------#
- set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
- set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
- set_location_assignment PIN_M1 -to RSTn
- set_location_assignment PIN_R9 -to CLK
- set_location_assignment PIN_J1 -to LED[0]
- set_location_assignment PIN_J2 -to LED[1]
- set_location_assignment PIN_K1 -to LED[2]
- set_location_assignment PIN_K2 -to LED[3]
复制代码 |
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