Debian-8+vivado 2016.2仿真使用2

哈哈欢

前言
        为了测试写的代码是否正确肯定要进行仿真，目前是使用VHDL语言进行开发，所以debian上VHDL仿真，暂时电脑存在 vivado 就是用他算了。
GHDL也能进行VHDL语言仿真，暂时不使用它。
准备：
工程代码下载地址：
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug937-design-files.zip
开始
   创建工程添加代码
   

添加完成就这个样子。
添加sine_high & sine_low & sine_mid ip  
   打开IP contalog  在找到DDS compiler 双击修改配置如图

  配置（英文描述）
      o Component Name: type sine_high
       o Configuration Options: select SIN COS LUT only
      o Noise Shaping: select None
      o Under Hardware Parameters, set Phase Width to 16 and Output Width to 20

On the Implementation tab, set Output Selection to Sine
On the Detailed Implementation tab, set Control Signals to ARESETn (active-Low)
下来是sine_mid

In the IP catalog, double-click the DDS Compiler IP a second time.
Specify the following on the Configuration tab:
o Component Name: type sine_mid
o Configuration Options: select SIN COS LUT only
o Noise Shaping: select None
o Under Hardware Parameters, set the Phase Width to 8, and the Output Width to 18
On the Implementation tab, set the Output Selection to Sine
On the Detailed Implementation tab, set Control Signals to ARESETn (active-Low)
Select the Summary tab, review the settings and click OK
下来增加sine_low ip

1.In the IP catalog, double-click the DDS Compiler IP for the third time.
2. Specify the following on the Configuration tab:
o Component Name: type sine_low
o Configuration Options: select SIN COS LUT only
o Noise Shaping: select None
o Under Hardware Parameters, set the Phase Width to 6 and the Output Width to 16
3. On the Implementation tab, set the Output Selection to Sine.
4. On the Detailed Implementation tab, set Control Signals to ARESETn (active-Low)
5. Select the Summary tab, review the settings as seen  and click OK.
下来行为仿真
在左边的project settings中选择如图的配置

选择好后点 rum simulation  （在左边的flow中），选择run behaiviroal  simulation
这里有个pre和post 过程。等等就好。
  结果

    学多少写多少。慢慢来。一次学不了那么多内容。