米尔 mys-y6ull-iot ，内核代码追踪

robe.zhang · 发表于 2018-9-8 00:36:36

内核总共就这么多，前面汇编太详细了，内核中间部分暂时不全，后面和驱动相关的部分写了：

/* =============================(arch/arm/kernel/head.S) */
(arch/arm/kernel/head.S):
#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
#define PG_DIR_SIZE 0x4000
#define PMD_ORDER 2
.equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
.macro pgtbl, rd, phys /* 宏定义 */
add \rd, \phys, #TEXT_OFFSET
sub \rd, \rd, #PG_DIR_SIZE
.endm
ENTRY(stext)
ARM_BE8(setend be ) @ ensure we are in BE8 mode
THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
bl __hyp_stub_install
safe_svcmode_maskall r9 /* safe_svcmode_maskall r9 */
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid
beq __error_p @ yes, error 'p'
blo __error_lpae @ only classic page table format
#ifndef CONFIG_XIP_KERNEL
adr r3, 2f
ldmia r3, {r4, r8}
sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
add r8, r8, r4 @ PHYS_OFFSET
#else
ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case
#endif
/*
* r1 = machine no, r2 = atags or dtb,
* r8 = phys_offset, r9 = cpuid, r10 = procinfo
*/
bl __vet_atags
#ifdef CONFIG_SMP_ON_UP
bl __fixup_smp
#endif
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
bl __fixup_pv_table
#endif
bl __create_page_tables
ldr r13, =__mmap_switched @ address to jump to after
@ mmu has been enabled
adr lr, BSYM(1f) @ return (PIC) address
mov r8, r4 @ set TTBR1 to swapper_pg_dir
ldr r12, [r10, #PROCINFO_INITFUNC]
add r12, r12, r10
ret r12
1: b __enable_mmu
ENDPROC(stext)
/* ============================= __hyp_stub_install (arch/arm/kernel/hyp-stub.S) */
ENTRY(__hyp_stub_install)
store_primary_cpu_mode r4, r5, r6 /* 保存primary_cpu模式到寄存器中 */
ENDPROC(__hyp_stub_install)
.macro store_primary_cpu_mode reg1, reg2, reg3
mrs \reg1, cpsr
and \reg1, \reg1, #MODE_MASK
adr \reg2, .L__boot_cpu_mode_offset
ldr \reg3, [\reg2]
str \reg1, [\reg2, \reg3]
.endm
/* ============================= safe_svcmode_maskall (arch/arm/include/asm/assembler.h)*/
.macro safe_svcmode_maskall reg:req
#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
mrs \reg , cpsr
eor \reg, \reg, #HYP_MODE
tst \reg, #MODE_MASK
bic \reg , \reg , #MODE_MASK
orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
THUMB( orr \reg , \reg , #PSR_T_BIT )
bne 1f
orr \reg, \reg, #PSR_A_BIT
adr lr, BSYM(2f)
msr spsr_cxsf, \reg
__MSR_ELR_HYP(14)
__ERET
1: msr cpsr_c, \reg
2:
#else
/*
* workaround for possibly broken pre-v6 hardware
* (akita, Sharp Zaurus C-1000, PXA270-based)
*/
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
#endif
.endm
/* ============================= __lookup_processor_type(arch/arm/kernel/head-common.S) */
/*
* Read processor ID register (CP#15, CR0), and look up in the linker-built
* supported processor list. Note that we can't use the absolute addresses
* for the __proc_info lists since we aren't running with the MMU on
* (and therefore, we are not in the correct address space). We have to
* calculate the offset.
*
* r9 = cpuid
* Returns:
* r3, r4, r6 corrupted
* r5 = proc_info pointer in physical address space
* r9 = cpuid (preserved)
*/
__lookup_processor_type:
adr r3, __lookup_processor_type_data
ldmia r3, {r4 - r6}
sub r3, r3, r4 @ get offset between virt&phys
add r5, r5, r3 @ convert virt addresses to
add r6, r6, r3 @ physical address space
1: ldmia r5, {r3, r4} @ value, mask
and r4, r4, r9 @ mask wanted bits
teq r3, r4
beq 2f
add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
cmp r5, r6
blo 1b
mov r5, #0 @ unknown processor
2: ret lr
ENDPROC(__lookup_processor_type)
/* ============================= __error_p (arch/arm/kernel/head-common.S)*/
__error_p:
#ifdef CONFIG_DEBUG_LL
adr r0, str_p1
bl printascii
mov r0, r9
bl printhex8
adr r0, str_p2
bl printascii
b __error
str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
str_p2: .asciz ").\n"
.align
#endif
ENDPROC(__error_p)
/* ============================= __error_lpae (arch/arm/kernel/head-common.S)*/
/* printascii,printhex8 (arch/arm/kernel/debug.S)*/
__error_lpae:
#ifdef CONFIG_DEBUG_LL
adr r0, str_lpae
bl printascii
b __error
str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
#else
b __error
#endif
.align
ENDPROC(__error_lpae)
/* ============================= __vet_atags(arch/arm/kernel/head-common.S) */
__vet_atags:
tst r2, #0x3 @ aligned?
bne 1f
ldr r5, [r2, #0]
#ifdef CONFIG_OF_FLATTREE
ldr r6, =OF_DT_MAGIC @ is it a DTB?
cmp r5, r6
beq 2f
#endif
cmp r5, #ATAG_CORE_SIZE @ is first tag ATAG_CORE?
cmpne r5, #ATAG_CORE_SIZE_EMPTY
bne 1f
ldr r5, [r2, #4]
ldr r6, =ATAG_CORE
cmp r5, r6
bne 1f
2: ret lr @ atag/dtb pointer is ok
1: mov r2, #0
ret lr
ENDPROC(__vet_atags)
/* ============================= __fixup_smp(arch/arm/kernel/head.S) */
__fixup_smp:
and r3, r9, #0x000f0000 @ architecture version
teq r3, #0x000f0000 @ CPU ID supported?
bne __fixup_smp_on_up @ no, assume UP
bic r3, r9, #0x00ff0000
bic r3, r3, #0x0000000f @ mask 0xff00fff0
mov r4, #0x41000000
orr r4, r4, #0x0000b000
orr r4, r4, #0x00000020 @ val 0x4100b020
teq r3, r4 @ ARM 11MPCore?
reteq lr @ yes, assume SMP
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
and r0, r0, #0xc0000000 @ multiprocessing extensions and
teq r0, #0x80000000 @ not part of a uniprocessor system?
bne __fixup_smp_on_up @ no, assume UP
@ Core indicates it is SMP. Check for Aegis SOC where a single
@ Cortex-A9 CPU is present but SMP operations fault.
mov r4, #0x41000000
orr r4, r4, #0x0000c000
orr r4, r4, #0x00000090
teq r3, r4 @ Check for ARM Cortex-A9
retne lr @ Not ARM Cortex-A9,
@ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
@ below address check will need to be #ifdef'd or equivalent
@ for the Aegis platform.
mrc p15, 4, r0, c15, c0 @ get SCU base address
teq r0, #0x0 @ '0' on actual UP A9 hardware
beq __fixup_smp_on_up @ So its an A9 UP
ldr r0, [r0, #4] @ read SCU Config
ARM_BE8(rev r0, r0) @ byteswap if big endian
and r0, r0, #0x3 @ number of CPUs
teq r0, #0x0 @ is 1?
retne lr
__fixup_smp_on_up:
adr r0, 1f
ldmia r0, {r3 - r5}
sub r3, r0, r3
add r4, r4, r3
add r5, r5, r3
b __do_fixup_smp_on_up
ENDPROC(__fixup_smp)
/* ========== */
__do_fixup_smp_on_up:
cmp r4, r5
reths lr
ldmia r4!, {r0, r6}
ARM( str r6, [r0, r3] )
THUMB( add r0, r0, r3 )
#ifdef __ARMEB__
THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
#endif
THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
THUMB( strh r6, [r0] )
b __do_fixup_smp_on_up
ENDPROC(__do_fixup_smp_on_up)
/* ============================= __fixup_pv_table (arch/arm/kernel/head.S)*/
__fixup_pv_table:
adr r0, 1f
ldmia r0, {r3-r7}
mvn ip, #0
subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
add r4, r4, r3 @ adjust table start address
add r5, r5, r3 @ adjust table end address
add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
add r7, r7, r3 @ adjust __pv_offset address
mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN
str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
mov r6, r3, lsr #24 @ constant for add/sub instructions
teq r3, r6, lsl #24 @ must be 16MiB aligned
THUMB( it ne @ cross section branch )
bne __error
str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits
b __fixup_a_pv_table
ENDPROC(__fixup_pv_table)
.align
1: .long .
.long __pv_table_begin
.long __pv_table_end
2: .long __pv_phys_pfn_offset
.long __pv_offset
.text
__fixup_a_pv_table:
adr r0, 3f
ldr r6, [r0]
add r6, r6, r3
ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
mov r6, r6, lsr #24
cmn r0, #1
#ifdef CONFIG_THUMB2_KERNEL
moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
lsls r6, #24
beq 2f
clz r7, r6
lsr r6, #24
lsl r6, r7
bic r6, #0x0080
lsrs r7, #1
orrcs r6, #0x0080
orr r6, r6, r7, lsl #12
orr r6, #0x4000
b 2f
1: add r7, r3
ldrh ip, [r7, #2]
ARM_BE8(rev16 ip, ip)
tst ip, #0x4000
and ip, #0x8f00
orrne ip, r6 @ mask in offset bits 31-24
orreq ip, r0 @ mask in offset bits 7-0
ARM_BE8(rev16 ip, ip)
strh ip, [r7, #2]
bne 2f
ldrh ip, [r7]
ARM_BE8(rev16 ip, ip)
bic ip, #0x20
orr ip, ip, r0, lsr #16
ARM_BE8(rev16 ip, ip)
strh ip, [r7]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
bcc 1b
bx lr
#else
#ifdef CONFIG_CPU_ENDIAN_BE8
moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
#else
moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
#endif
b 2f
1: ldr ip, [r7, r3]
#ifdef CONFIG_CPU_ENDIAN_BE8
@ in BE8, we load data in BE, but instructions still in LE
bic ip, ip, #0xff000000
tst ip, #0x000f0000 @ check the rotation field
orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
biceq ip, ip, #0x00004000 @ clear bit 22
orreq ip, ip, r0 @ mask in offset bits 7-0
#else
bic ip, ip, #0x000000ff
tst ip, #0xf00 @ check the rotation field
orrne ip, ip, r6 @ mask in offset bits 31-24
biceq ip, ip, #0x400000 @ clear bit 22
orreq ip, ip, r0 @ mask in offset bits 7-0
#endif
str ip, [r7, r3]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
bcc 1b
ret lr
#endif
ENDPROC(__fixup_a_pv_table)
/* ============================= __create_page_tables (arch/arm/kernel/head.S)*/
__create_page_tables:
pgtbl r4, r8 @ page table address
/*
* Clear the swapper page table
*/
mov r0, r4
mov r3, #0
add r6, r0, #PG_DIR_SIZE
1: str r3, [r0], #4
str r3, [r0], #4
str r3, [r0], #4
str r3, [r0], #4
teq r0, r6
bne 1b
#ifdef CONFIG_ARM_LPAE
/*
* Build the PGD table (first level) to point to the PMD table. A PGD
* entry is 64-bit wide.
*/
mov r0, r4
add r3, r4, #0x1000 @ first PMD table address
orr r3, r3, #3 @ PGD block type
mov r6, #4 @ PTRS_PER_PGD
mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
1:
#ifdef CONFIG_CPU_ENDIAN_BE8
str r7, [r0], #4 @ set top PGD entry bits
str r3, [r0], #4 @ set bottom PGD entry bits
#else
str r3, [r0], #4 @ set bottom PGD entry bits
str r7, [r0], #4 @ set top PGD entry bits
#endif
add r3, r3, #0x1000 @ next PMD table
subs r6, r6, #1
bne 1b
add r4, r4, #0x1000 @ point to the PMD tables
#ifdef CONFIG_CPU_ENDIAN_BE8
add r4, r4, #4 @ we only write the bottom word
#endif
#endif
ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
/*
* Create identity mapping to cater for __enable_mmu.
* This identity mapping will be removed by paging_init().
*/
adr r0, __turn_mmu_on_loc
ldmia r0, {r3, r5, r6}
sub r0, r0, r3 @ virt->phys offset
add r5, r5, r0 @ phys __turn_mmu_on
add r6, r6, r0 @ phys __turn_mmu_on_end
mov r5, r5, lsr #SECTION_SHIFT
mov r6, r6, lsr #SECTION_SHIFT
1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
cmp r5, r6
addlo r5, r5, #1 @ next section
blo 1b
/*
* Map our RAM from the start to the end of the kernel .bss section.
*/
add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
ldr r6, =(_end - 1)
orr r3, r8, r7
add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
1: str r3, [r0], #1 << PMD_ORDER
add r3, r3, #1 << SECTION_SHIFT
cmp r0, r6
bls 1b
#ifdef CONFIG_XIP_KERNEL
/*
* Map the kernel image separately as it is not located in RAM.
*/
#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
mov r3, pc
mov r3, r3, lsr #SECTION_SHIFT
orr r3, r7, r3, lsl #SECTION_SHIFT
add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
ldr r6, =(_edata_loc - 1)
add r0, r0, #1 << PMD_ORDER
add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
1: cmp r0, r6
add r3, r3, #1 << SECTION_SHIFT
strls r3, [r0], #1 << PMD_ORDER
bls 1b
#endif
/*
* Then map boot params address in r2 if specified.
* We map 2 sections in case the ATAGs/DTB crosses a section boundary.
*/
mov r0, r2, lsr #SECTION_SHIFT
movs r0, r0, lsl #SECTION_SHIFT
subne r3, r0, r8
addne r3, r3, #PAGE_OFFSET
addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
orrne r6, r7, r0
strne r6, [r3], #1 << PMD_ORDER
addne r6, r6, #1 << SECTION_SHIFT
strne r6, [r3]
#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
sub r4, r4, #4 @ Fixup page table pointer
@ for 64-bit descriptors
#endif
#ifdef CONFIG_DEBUG_LL
#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
/*
* Map in IO space for serial debugging.
* This allows debug messages to be output
* via a serial console before paging_init.
*/
addruart r7, r3, r0
mov r3, r3, lsr #SECTION_SHIFT
mov r3, r3, lsl #PMD_ORDER
add r0, r4, r3
mov r3, r7, lsr #SECTION_SHIFT
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
orr r3, r7, r3, lsl #SECTION_SHIFT
#ifdef CONFIG_ARM_LPAE
mov r7, #1 << (54 - 32) @ XN
#ifdef CONFIG_CPU_ENDIAN_BE8
str r7, [r0], #4
str r3, [r0], #4
#else
str r3, [r0], #4
str r7, [r0], #4
#endif
#else
orr r3, r3, #PMD_SECT_XN
str r3, [r0], #4
#endif
#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
/* we don't need any serial debugging mappings */
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
#endif
#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
/*
* If we're using the NetWinder or CATS, we also need to map
* in the 16550-type serial port for the debug messages
*/
add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
orr r3, r7, #0x7c000000
str r3, [r0]
#endif
#ifdef CONFIG_ARCH_RPC
/*
* Map in screen at 0x02000000 & SCREEN2_BASE
* Similar reasons here - for debug. This is
* only for Acorn RiscPC architectures.
*/
add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
orr r3, r7, #0x02000000
str r3, [r0]
add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
str r3, [r0]
#endif
#endif
#ifdef CONFIG_ARM_LPAE
sub r4, r4, #0x1000 @ point to the PGD table
mov r4, r4, lsr #ARCH_PGD_SHIFT
#endif
ret lr
ENDPROC(__create_page_tables)
/* ============================= __mmap_switched(arch/arm/kernel/head-common.S) */
__mmap_switched:
adr r3, __mmap_switched_data
ldmia r3!, {r4, r5, r6, r7}
cmp r4, r5 @ Copy data segment if needed
1: cmpne r5, r6
ldrne fp, [r4], #4
strne fp, [r5], #4
bne 1b
mov fp, #0 @ Clear BSS (and zero fp)
1: cmp r6, r7
strcc fp, [r6],#4
bcc 1b
ARM( ldmia r3, {r4, r5, r6, r7, sp})
THUMB( ldmia r3, {r4, r5, r6, r7} )
THUMB( ldr sp, [r3, #16] )
str r9, [r4] @ Save processor ID
str r1, [r5] @ Save machine type
str r2, [r6] @ Save atags pointer
cmp r7, #0
strne r0, [r7] @ Save control register values
b start_kernel
ENDPROC(__mmap_switched)
.align 2
.type __mmap_switched_data, %object
__mmap_switched_data:
.long __data_loc @ r4
.long _sdata @ r5
.long __bss_start @ r6
.long _end @ r7
.long processor_id @ r4
.long __machine_arch_type @ r5
.long __atags_pointer @ r6
#ifdef CONFIG_CPU_CP15
.long cr_alignment @ r7
#else
.long 0 @ r7
#endif
.long init_thread_union + THREAD_START_SP @ sp
.size __mmap_switched_data, . - __mmap_switched_data
/* ============================= __enable_mmu (arch/arm/kernel/head.S)*/
/*
* Setup common bits before finally enabling the MMU. Essentially
* this is just loading the page table pointer and domain access
* registers.
*
* r0 = cp#15 control register
* r1 = machine ID
* r2 = atags or dtb pointer
* r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
* r9 = processor ID
* r13 = *virtual* address to jump to upon completion
*/
__enable_mmu:
#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
orr r0, r0, #CR_A
#else
bic r0, r0, #CR_A
#endif
#ifdef CONFIG_CPU_DCACHE_DISABLE
bic r0, r0, #CR_C
#endif
#ifdef CONFIG_CPU_BPREDICT_DISABLE
bic r0, r0, #CR_Z
#endif
#ifdef CONFIG_CPU_ICACHE_DISABLE
bic r0, r0, #CR_I
#endif
#ifndef CONFIG_ARM_LPAE
mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r5, c3, c0, 0 @ load domain access register
mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
#endif
b __turn_mmu_on
ENDPROC(__enable_mmu)
/*
* Enable the MMU. This completely changes the structure of the visible
* memory space. You will not be able to trace execution through this.
* If you have an enquiry about this, *please* check the linux-arm-kernel
* mailing list archives BEFORE sending another post to the list.
*
* r0 = cp#15 control register
* r1 = machine ID
* r2 = atags or dtb pointer
* r9 = processor ID
* r13 = *virtual* address to jump to upon completion
*
* other registers depend on the function called upon completion
*/
.align 5
.pushsection .idmap.text, "ax"
ENTRY(__turn_mmu_on)
mov r0, r0
instr_sync
mcr p15, 0, r0, c1, c0, 0 @ write control reg
mrc p15, 0, r3, c0, c0, 0 @ read id reg
instr_sync
mov r3, r3
mov r3, r13
ret r3
__turn_mmu_on_end:
ENDPROC(__turn_mmu_on)
/*================头文件 */
#include "head-common.S"
#include <asm/assembler.h>
/*=================================================start_kernel (init/main.c:) */
lockdep_init: 初始化 (2^12个)classhash_table 链表头
初始化 (2^15个)chainhash_table 链表头
全局静态变量置1
rest_init
kernel_init
kernel_init_freeable
do_basic_setup
driver_init
void __init driver_init(void)
{
/* These are the core pieces */
devtmpfs_init();
devices_init();
buses_init();
classes_init();
firmware_init();
hypervisor_init();
/* These are also core pieces, but must come after the
* core core pieces.
*/
platform_bus_init();
cpu_dev_init();
memory_dev_init();
container_dev_init();
of_core_init();
}

复制代码

第二部部分是整理好的链接文件，对着看：

/* arch/arm/kernel/vmlinux.lds
* Automatically generated file; DO NOT EDIT.
* Linux/arm 4.1.15 Kernel Configuration
*/
OUTPUT_ARCH(arm)
ENTRY(stext)
jiffies = jiffies_64;
SECTIONS
{
/*
* XXX: The linker does not define how output sections are
* assigned to input sections when there are multiple statements
* matching the same input section name. There is no documented
* order of matching.
*
* unwind exit sections must be discarded before the rest of the
* unwind sections get included.
*/
/DISCARD/ : {
*(.ARM.exidx.exit.text)
*(.ARM.extab.exit.text)
*(.exitcall.exit)
*(.discard)
*(.discard.*)
}
. = 0x80000000 + 0x00008000;
.head.text : {
_text = .; *(.head.text)
}
.text : { /* Real text segment */
_stext = .; /* Text and read-only data */
. = ALIGN(8); __idmap_text_start = .; *(.idmap.text)
__idmap_text_end = .;
. = ALIGN((1 << 12));
__hyp_idmap_text_start = .;
*(.hyp.idmap.text)
__hyp_idmap_text_end = .;
__exception_text_start = .;
*(.exception.text)
__exception_text_end = .;
. = ALIGN(8); *(.text.hot)
*(.text .text.fixup)
*(.ref.text)
*(.text.unlikely)
. = ALIGN(8); __sched_text_start = .;
*(.sched.text)
__sched_text_end = .;
. = ALIGN(8); __lock_text_start = .; *(.spinlock.text)
__lock_text_end = .;
. = ALIGN(8); __kprobes_text_start = .;
*(.kprobes.text)
__kprobes_text_end = .;
*(.gnu.warning)
*(.glue_7)
*(.glue_7t)
. = ALIGN(4); *(.got) /* Global offset table */
. = ALIGN(4); __proc_info_begin = .; *(.proc.info.init)
__proc_info_end = .;
}
. = ALIGN(((1 << 12)));
.rodata : AT(ADDR(.rodata) - 0) {
__start_rodata = .; *(.rodata) /* start of rodata section */
*(.rodata.*)
*(__vermagic)
. = ALIGN(8); __start___tracepoints_ptrs = .;
*(__tracepoints_ptrs)
__stop___tracepoints_ptrs = .;
*(__tracepoints_strings)
}
.rodata1 : AT(ADDR(.rodata1) - 0) { *(.rodata1)
}
. = ALIGN(8);
__bug_table : AT(ADDR(__bug_table) - 0) {
__start___bug_table = .;
*(__bug_table)
__stop___bug_table = .;
}
.pci_fixup : AT(ADDR(.pci_fixup) - 0) {
__start_pci_fixups_early = .;
*(.pci_fixup_early)
__end_pci_fixups_early = .;
__start_pci_fixups_header = .;
*(.pci_fixup_header)
__end_pci_fixups_header = .;
__start_pci_fixups_final = .;
*(.pci_fixup_final)
__end_pci_fixups_final = .;
__start_pci_fixups_enable = .;
*(.pci_fixup_enable)
__end_pci_fixups_enable = .;
__start_pci_fixups_resume = .;
*(.pci_fixup_resume)
__end_pci_fixups_resume = .;
__start_pci_fixups_resume_early = .;
*(.pci_fixup_resume_early)
__end_pci_fixups_resume_early = .;
__start_pci_fixups_suspend = .;
*(.pci_fixup_suspend)
__end_pci_fixups_suspend = .;
__start_pci_fixups_suspend_late = .;
*(.pci_fixup_suspend_late)
__end_pci_fixups_suspend_late = .;
}
.builtin_fw : AT(ADDR(.builtin_fw) - 0) {
__start_builtin_fw = .; *(.builtin_fw)
__end_builtin_fw = .;
}
/* >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> syscall 用的 >>>>>>>>>>>>>>> */
__ksymtab : AT(ADDR(__ksymtab) - 0) {
__start___ksymtab = .; *(SORT(___ksymtab+*))
__stop___ksymtab = .;
}
__ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - 0) {
__start___ksymtab_gpl = .;
*(SORT(___ksymtab_gpl+*))
__stop___ksymtab_gpl = .;
}
__ksymtab_unused : AT(ADDR(__ksymtab_unused) - 0) {
__start___ksymtab_unused = .;
*(SORT(___ksymtab_unused+*))
__stop___ksymtab_unused = .;
}
__ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - 0) {
__start___ksymtab_unused_gpl = .;
*(SORT(___ksymtab_unused_gpl+*))
__stop___ksymtab_unused_gpl = .;
}
__ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - 0) {
__start___ksymtab_gpl_future = .;
*(SORT(___ksymtab_gpl_future+*))
__stop___ksymtab_gpl_future = .;
}
__kcrctab : AT(ADDR(__kcrctab) - 0) {
__start___kcrctab = .; *(SORT(___kcrctab+*))
__stop___kcrctab = .;
}
__kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - 0) {
__start___kcrctab_gpl = .;
*(SORT(___kcrctab_gpl+*))
__stop___kcrctab_gpl = .;
}
__kcrctab_unused : AT(ADDR(__kcrctab_unused) - 0) {
__start___kcrctab_unused = .;
*(SORT(___kcrctab_unused+*))
__stop___kcrctab_unused = .;
}
__kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - 0) {
__start___kcrctab_unused_gpl = .;
*(SORT(___kcrctab_unused_gpl+*))
__stop___kcrctab_unused_gpl = .;
}
__kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - 0) {
__start___kcrctab_gpl_future = .;
*(SORT(___kcrctab_gpl_future+*))
__stop___kcrctab_gpl_future = .;
}
__ksymtab_strings : AT(ADDR(__ksymtab_strings) - 0) {
*(__ksymtab_strings)
}
/* <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< syscall 用的 <<<<<<<<<<<<<<<<<<<<< */
__init_rodata : AT(ADDR(__init_rodata) - 0) {
*(.ref.rodata)
}
__param : AT(ADDR(__param) - 0) {
__start___param = .;
*(__param)
__stop___param = .;
}
__modver : AT(ADDR(__modver) - 0) {
__start___modver = .; *(__modver)
__stop___modver = .;
. = ALIGN(((1 << 12)));
__end_rodata = .; /* End of rodata section */
}
. = ALIGN(((1 << 12)));
. = ALIGN(4);
__ex_table : AT(ADDR(__ex_table) - 0) {
__start___ex_table = .; *(__ex_table)
__stop___ex_table = .;
}
/*
* Stack unwinding tables
*/
. = ALIGN(8);
.ARM.unwind_idx : { __start_unwind_idx = .; *(.ARM.exidx*)
__stop_unwind_idx = .;
}
.ARM.unwind_tab : { __start_unwind_tab = .; *(.ARM.extab*)
__stop_unwind_tab = .;
}
.notes : AT(ADDR(.notes) - 0) {
__start_notes = .; *(.note.*)
__stop_notes = .;
}
_etext = .; /* End of text and rodata section */
. = ALIGN((1 << 12));
__init_begin = .;
/*
* The vectors and stubs are relocatable code, and the
* only thing that matters is their relative offsets
*/
__vectors_start = .;
.vectors 0 : AT(__vectors_start) {
*(.vectors)
}
. = __vectors_start + SIZEOF(.vectors);
__vectors_end = .;
__stubs_start = .;
.stubs 0x1000 : AT(__stubs_start) {
*(.stubs)
}
. = __stubs_start + SIZEOF(.stubs);
__stubs_end = .;
. = ALIGN(8);
.init.text : AT(ADDR(.init.text) - 0) {
_sinittext = .; *(.init.text)
*(.meminit.text)
_einittext = .;
}
.exit.text : {
*(.exit.text)
*(.memexit.text)
}
.init.proc.info : {
}
.init.arch.info : {
__arch_info_begin = .;
*(.arch.info.init)
__arch_info_end = .;
}
.init.tagtable : {
__tagtable_begin = .;
*(.taglist.init)
__tagtable_end = .;
}
.init.smpalt : {
__smpalt_begin = .;
*(.alt.smp.init)
__smpalt_end = .;
}
.init.pv_table : {
__pv_table_begin = .;
*(.pv_table)
__pv_table_end = .;
}
.init.data : { *(.init.data)
*(.meminit.data)
*(.init.rodata)
*(.meminit.rodata)
. = ALIGN(8); __clk_of_table = .; *(__clk_of_table)
*(__clk_of_table_end)
. = ALIGN(8); __reservedmem_of_table = .;
*(__reservedmem_of_table)
*(__reservedmem_of_table_end)
. = ALIGN(8); __clksrc_of_table = .; *(__clksrc_of_table)
*(__clksrc_of_table_end)
. = ALIGN(8); __cpu_method_of_table = .;
*(__cpu_method_of_table)
*(__cpu_method_of_table_end)
. = ALIGN(8); __cpuidle_method_of_table = .;
*(__cpuidle_method_of_table)
*(__cpuidle_method_of_table_end)
. = ALIGN(32); __dtb_start = .; *(.dtb.init.rodata) __dtb_end = .;
. = ALIGN(8); __irqchip_of_table = .; *(__irqchip_of_table)
*(__irqchip_of_table_end)
. = ALIGN(16); __setup_start = .; *(.init.setup) __setup_end = .;
__initcall_start = .; *(.initcallearly.init) __initcall0_start = .;
*(.initcall0.init)
*(.initcall0s.init)
__initcall1_start = .; *(.initcall1.init)
*(.initcall1s.init)
__initcall2_start = .; *(.initcall2.init)
*(.initcall2s.init)
__initcall3_start = .; *(.initcall3.init)
*(.initcall3s.init)
__initcall4_start = .; *(.initcall4.init)
*(.initcall4s.init)
__initcall5_start = .; *(.initcall5.init)
*(.initcall5s.init)
__initcallrootfs_start = .;
*(.initcallrootfs.init)
*(.initcallrootfss.init)
__initcall6_start = .; *(.initcall6.init)
*(.initcall6s.init)
__initcall7_start = .; *(.initcall7.init)
*(.initcall7s.init)
__initcall_end = .;
__con_initcall_start = .;
*(.con_initcall.init)
__con_initcall_end = .;
__security_initcall_start = .;
*(.security_initcall.init)
__security_initcall_end = .;
. = ALIGN(4); __initramfs_start = .; *(.init.ramfs)
. = ALIGN(8); *(.init.ramfs.info)
}
.exit.data : {
*(.exit.data)
*(.memexit.data)
*(.memexit.rodata)
}
. = ALIGN((1 << 12));
.data..percpu : AT(ADDR(.data..percpu) - 0) {
__per_cpu_load = .;
__per_cpu_start = .; *(.data..percpu..first)
. = ALIGN((1 << 12)); *(.data..percpu..page_aligned)
. = ALIGN((1 << 6)); *(.data..percpu..read_mostly)
. = ALIGN((1 << 6)); *(.data..percpu)
*(.data..percpu..shared_aligned)
__per_cpu_end = .;
}
. = ALIGN(((1 << 12) << 1));
__init_end = .;
__data_loc = .;
.data : AT(__data_loc) {
_data = .; /* address in memory */
_sdata = .;
/*
* first, the init task union, aligned
* to an 8192 byte boundary.
*/
. = ALIGN(((1 << 12) << 1)); *(.data..init_task)
. = ALIGN((1 << 12));
__nosave_begin = .;
*(.data..nosave)
. = ALIGN((1 << 12));
__nosave_end = .;
. = ALIGN((1 << 6)); *(.data..cacheline_aligned)
. = ALIGN((1 << 6)); *(.data..read_mostly)
. = ALIGN((1 << 6));
/*
* and the usual data section
*/
*(.data)
*(.ref.data)
*(.data..shared_aligned)
*(.data.unlikely)
. = ALIGN(32); *(__tracepoints)
. = ALIGN(8); __start___jump_table = .;
*(__jump_table)
__stop___jump_table = .;
. = ALIGN(8); __start___verbose = .; *(__verbose)
__stop___verbose = .;
CONSTRUCTORS
_edata = .;
}
_edata_loc = __data_loc + SIZEOF(.data);
. = ALIGN(0); __bss_start = .;
. = ALIGN(0);
.sbss : AT(ADDR(.sbss) - 0) { *(.sbss)
*(.scommon)
}
. = ALIGN(0);
.bss : AT(ADDR(.bss) - 0) { *(.bss..page_aligned)
*(.dynbss)
*(.bss)
*(COMMON)
}
. = ALIGN(0); __bss_stop = .;
_end = .;
.stab 0 : { *(.stab)
}
.stabstr 0 : { *(.stabstr)
}
.stab.excl 0 : { *(.stab.excl)
}
.stab.exclstr 0 : { *(.stab.exclstr)
}
.stab.index 0 : { *(.stab.index)
}
.stab.indexstr 0 : { *(.stab.indexstr)
}
.comment 0 : { *(.comment)
}
}
/*
* These must never be empty
* If you have to comment these two assert statements out, your
* binutils is too old (for other reasons as well)
*/
ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
/*
* The HYP init code can't be more than a page long,
* and should not cross a page boundary.
* The above comment applies as well.
*/
ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & (~((1 << 12) - 1))) <= (1 << 12),
"HYP init code too big or misaligned")

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[原创] 米尔 mys-y6ull-iot ，内核代码追踪

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