high-voltage ESD papers

caroline11

1. High-voltage nLDMOS in waffle-layout style with body-injected technique for ESD protection
2. Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)
3. Source-side engineering to increase holding voltage of LDMOS in a 0.5-um 16-V BCD technology to avoid latch-up failure
4. Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
5. Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration