CMOS ADC with 82 dB SFDR

caroline11

A recent trend in cellular basestation design is to digitize multiple channels with a single ADC, often at the intermediate frequency
(IF). This requires an ADC with wide dynamic range, particularly SFDR above 80dB and SNR better than 70dB, even when sampling input frequencies above 70MHz. This 12b, 65MSample/s (MSPS) ADC incorporates a wide-bandwidth, low-distortion input stage coupled with a digitally-calibrated, multibit pipeline architecture optimized for low power consumption。